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EECS 470 is an advanced undergraduate/introductory graduate-level course in computer architecture.
EECS 470 is an advanced undergraduate/introductory graduate-level course in computer architecture.
This class is intended to do two things:
This class is intended to do two things:
1. To give a solid, detailed understanding of how computers are designed and implemented, including the central processor and memory
1. To give a solid, detailed understanding of how computers are designed and implemented, including the central processor and memory
2. To provide awareness of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems.
2. To provide awareness of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems.
It covers pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), operating system issues, and basic multiprocessor systems.
It covers pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), operating system issues, and basic multiprocessor systems.
A central part of EECS 470 is the detailed design of major portions of a substantial out-of-order processor using the Verilog hardware design language (HDL) along with modern commercial CAD tools to develop the design.
A central part of EECS 470 is the detailed design of major portions of a substantial out-of-order processor using the Verilog hardware design language (HDL) along with modern commercial CAD tools to develop the design.
Architecture Design
Architecture Design
There are several microarchitecture design choices and advanced features involved in our RISC-V out-of-order processor:
Intel P6-style register renaming
Two-way superscalar
Early branch recovery
Next-line instruction cache prefetching
Gshare branch predictor and branch target buffer
Return address stack
Store queue with store-to-load forwarding
Non-blocking writeback data cache
Performance Evaluation
Performance Evaluation
Our processor was successfully able to pass all instructor test cases and synthesize at a 40 MHz clock frequency.
Below is our performance relative to the class:
Final Report
Final Report
Final Report.pdfPage updated
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