Designing a hardware accelerator for machine learning application. Planning to tapeout the chip and validate the design.
During my initial 5-6 months as an Associate Verification Engineer at Micron, I focused on Timing Accurate Verilog RNX verification (X-Propagation). This involved analyzing GLS netlists to identify and debug timing failures. I traced the source of 'X' signals, determined the root cause (often timing differences between JSS/JFF/TT netlists, setup/hold violations, or Clock Domain Crossing issues), and recommended design changes or sign-offs. I mostly conducted numerous read/write path debugs.
Next I joined the Async-TB verification team, focusing on Refresh Circuit verification. As Refresh Operations lack a direct output on the IO Pad, verification centered on checking internal control signals, DRAM array, and Sense Amplifier functionality across all refresh modes. I employed verification techniques like monitors, scoreboards, assertions, and coverage to model WordLine and BitLine behavior. This encompassed testing operations such as Activate, Write, Read, Precharge, Repair (row/column), refresh/self-refresh/row-hammer-refresh, compression, and Testmode features for DFT. I developed dedicated test patterns to rigorously exercise all checkers, in addition to utilizing random patterns.
I contributed to the cutting-edge HBM3E design, establishing a new verification infrastructure for multi-channel, multi-stack scenarios. Initially mentored, I later independently drove this critical flow, consistently adapting to project demands. I successfully closed all verification gaps prior to tapeout, delivering a bug-free design. This achievement led to my promotion.
Subsequently, I led the Async-TB team for a 2-channel LPDDR5 project, mentoring and guiding a team of 3 engineers. I spearheaded improvements in the verification flow, enhancing coverage, assertions, code coverage, and flow automation. I implemented automations for binning fail signatures and accelerating reruns, saving nearly 3 hours daily. Leveraging prior project experience and team support, I honed my soft skills in mentorship and communication. This resulted in my promotion to Senior Engineer.
Finally, I led Async-TB for another LPDDR5 project while concurrently exploring AI initiatives and Automation with our Director. My contributions to enhancing verification, closing coverage gaps, and implementing automation are recognized through two disclosures.
Developed the microarchitecture for FPGA implementation of CCSDS123-B2 image compression algorithm using MATLAB. Tested the algorithm by designing a compression and decompression engine on Matlab. Designed a parameterized, pipelined image compression core in Verilog. Performed block level verification of the design using the MATLAB model for each stage output.
Updated the firmware of an FPGA-based data acquisition board to collect motor’s vibration data using an accelerometer sensor and sent it to a remote host via Ethernet; performed spectral analysis and classification for preventive maintenance.