Motivation:
Studied the challenges in testing VLSI circuits. The exponential growth of testing time with increase in Primary Input, FlipFlops and combinational circuits make it impossible to test all the patterns on a fabricated chip. Hence it becomes necessary to forget about 100% functional testing and rely on fault models and have high coverage for those fault models.
Fault Models:
Studied different fault models like SA0/SA1 fault, bridging fault, crossover fault, Stuck Open/Stuck Short fault etc. We reviewed equivalent and dominance of faults, reducing the total number of faults we need to test for exhaustive coverage. Studied the Ruth’s ATPG algorithm (D algorithm) in detail. For a given fault model, learnt how to sensitise the fault, justify and propagate it to a primary output. Reviewed how redundancy in the circuit can prevent the fault to propagate to the output, making certain faults untestable. Studied some advance ATPG algorithms like FAN(breadth first search, unique sensitisation), PODEM(Depth First Search, assignment only at primary input) and Socrates(static implications).
Fault Simulation:
During fault simulation, a test vector generated for one fault model can also detect other faults. We need to make modifications to our netlist to model the fault and run the test vector to see if the output is different from the correct behaviour. Hence to identify test vectors for all the faults, we do not need to run ATPG algorithm on all the faults, because tests for one fault can also catch other faults. There are 2 other approaches to run fault simulation, parallel fault simulation and deductive fault simulation. While parallel fault simulation uses larger word size of computers to model multiple faults and generate outputs in one pass, the fault simulator cannot drop the faults till all the faults have a test vector associated with them. Deductive fault simulation uses set algebra to calculate which faults will be identified by one particular test vector. Deductive fault simulation also uses event driven simulation, which reduces the recalculation of a certain branch in a circuit if there is no change in its inputs. Event driven simulation is also able to model timing delays of the gates. Hence deductive fault simulation is much more robust.
Sequential Circuit Testing:
We reviewed sequential circuit testing, and how it becomes difficult to set the correct and faulty machines to the same initial state, and then to a state with differing outputs. Muth’s 9 valued algebra and S-graph were some tools used to analyse these circuits more effectively. However the challenge for sequential circuits are still not solved with them completely.
DFT:
By adding minor changes to the design (DFT), we were able to address the problems in the sequential testing, and do it as efficiently as combinational testing. We studies about scan chains, partial scan chains, parallel/serial chains, MISR(output compression), input compression etc. We made decisions about which FF to include in the scan chain to break cyclicality of the S graph.
Conclusion:
Overall the course gave a comprehensive idea of generating tests for circuits, problems which prevent this from happening very effectively, and DFT methodology to fix some of those problems. DFT and tests takes about 10-15% of cost of silicon fabrication and testing process, and efficient algorithms and design tradeoffs can significantly improve cost margins and design robustness.
Studied complete VLSI design flow in this course. Below are the topics which were covered:
RTL, spice and AMS simulation.
RTL coding best practices for synthesis and FSM.
STA analysis, correlation with Miller Effect.
Synthesis(Synopsys Design Compiler) and PNR (cadence Innovus) flow using TSMC 65nm tech library. Studied all steps in the automated design flow, from floorplanning, power planning (stripe and power ring addition), pin placement, placement, clock tree synthesis and routing. Hierarchical Synthesis and PNR (generating Hard macros). Adding DCAP and Filler to mitigate power bounce.
Advanced Topics: High Speed: Pipelining and multicycle paths. Low power: Pipelining and DVFS (Dynamic Voltage and Frequency Scaling). Memory (6T/8TSRAM) and Memory compiler. Asynchronous Boundary Interactions, synchronizers. Dynamic Power Calculation with Innovus (Voltus). SDF annotated Gate Level Simulations.
Studied many neuromorphic computing models/quantum computers and physical self organising devices. This course was very broad and all students had to write a review/research paper on a topic of their choice. I reviewed the topic of "HyperDimentional Computing".
Studied historical trends and future direction of Computer Architecture. Amdahl's Law, Iron law of processor performance, Dark silicon and future perspective, i.e. emphasis on low energy. Analysed MIPS single cycle, multi cycle, 5 stage and variable stage processor with hazard detection and forwarding, Branch predictors. Multi level cache hierarchies, victim cache, replacement schemes, prefetching etc.
Studied VLSI design choices for high speed digital circuit design. Learned CMOS circuit theory, and non-linear effects, followed by Elmore's delay model, sizing and logical effort estimation.
Combinational Circuits: Studied different circuit families like static CMOS, pseudo NMOS, ratioed logic, Domino logic etc.
Sequential Circuits: Learned design and timing considerations of all standard blocks like Latch, FlipFlop, pulsed latch etc.
Datapath: Designed adders and multipliers. Explored multiple design options (Carry Save Adder, Carry Lookahead Adder, Ripple Carry Adder, etc) and algorithms like booth's algorithm for radix 2 multiplication.
Labs: Used Cadence Virtuoso with NCSU 45nm tech lib for the design.
Learned Neural Networks training on Pytorch environment for various models like ResNet, VGG.
Learned techniques like quantisation, structured/unstructured sparsity, batch normalisation etc on PyTorch through course labs.
Learned abut systolic array architectures, and how to reuse weight and activations in systolic array to minimise data movement. Weight stationary and output stationary architecture.
Explored some challenges in the Transformer architectures, and bottlenecks in using 2D systolic array with it.