Week 3 - (9/15/20)

• Read: Chapters 5 & 6 of Textbook: Free Range VHDL

  • 5. Standard Models in VHDL Architectures

    • Introduces the Data-flow and Behavioral Style Architecture models as well as sequential and process statements

  • 6. VHDL Operators

    • Introduces Logical, Relational, Shift, Concatenation, Modulus and Remainder, as well as various other, operators

• Worked through various GHDL examples:

  • Hello

  • Half Adder

  • Full Adder

  • D flip-flop

  • T flip-flop

Half adder example (followed from: Nerdy Dave)

• First create ha.vhdl file which contains the half adder functionality

• Next create the ha_tb.vhdl file which tests the functionality by verifying each case for the inputs

• In the terminal, use ghdl (with flags '-s', '-a', '-e', '-r') to check the syntax of the file, analyze the file, to elaborate the unit in the file (and create its executable) and to run it

• Next, run 'ghdl -r ha_tb --vcd=ha.vcd' which will create the gtkwave compatible file to view to functionality on a waveform generator

A half adder has 2 inputs (in this case: A, B) and two outputs (sum and carry)

The process was repeated for the adder example (followed from: link)

The adder has three inputs (2 bits and a carry-in) and two outputs (sum and a carry-out)

The process was repeated for the D Flip-Flop example (followed from: link)

The process was repeated for the T Flip-Flop example (followed from: link)