CPE 487
GitHub Link Down Below
Embedded Files
Alternatively, you can click the link below to go to the repo:
Reports
Reports
[2021-10-04] Completed Assignment 2 (Creating test bench for a VHDL program). Uploaded on GitHub.
[2021-10-05] Reinstalled Vivado (It turns out that I didn't have to do this). I did the following process to get the board file to appear.
If Board Files Not Appearing:
Go to the Digilent/vivado-boards/new/board_files page on GitHub: https://github.com/Digilent/vivado-boards/tree/master/new/board_files
Find your board (nexys-a7-100t/D.0 for me) and download that directory.
Find your Xilinx folder on your computer that you created when you installed Vivado.
Go into Xilinx/Vivado/2021.1/data/boards/board_files and place your board's directory that you just downloaded into the board_files folder.
This board should now appear in the boards list when you have to select a board when you create a new project in Vivado.
Once I installed the correct board files, I was able to complete Project 1 of Lab 1.
Below is a carousel of pictures of all the switch configurations for Project 1 of Lab 1
[2021-10-07] Finished Lab 1 Project 2 and Lab 2. Below I have the videos of the single-digit hex counter from Lab 1 Project 2 and the four-digit hex counter from Lab 2. Unfortunately, I did not capture a video of the FPGA running the eight-digit hex counter modifications.
Single digit hex counter.MOVSingle Digit Hex Counter
https://drive.google.com/file/d/1wVDoMl3xekpqSeAMw61V_yB2p-gYnQd9/view?usp=sharing
4 Digit hex counter.MOVFour Digit Hex Counter
https://drive.google.com/file/d/1MNuL3Kn0D2lxanf4e9LdOdYXUbWTgFlj/view?usp=sharing
[2021-10-12] Finished Lab 2 and Lab 3. Made appropriate modifications to hex calculator. Pictures of FPGA and peripherals shown below. Also made modifications to bouncing ball lab.
Lab 3.MOVVideo of Modified Bouncing Ball
https://drive.google.com/file/d/1Ld-E-uMI-ALWMGu0Xsm9iYQNwa8yqiIO/view?usp=sharing
[2021-10-14] Finished Lab 4. I modified the bouncing ball code on my own to change the color of the ball, change the shape of the ball into bigger and smaller squared, and make the ball move in both the x and y directions. I got stuck when trying to make the ball round and then I learned that there were modifications already made on those files on GitHub for us to use. I then uploaded the given modified code to the FPGA, and it worked with the ball being round, a different color, and moving in both the x and y directions. From what I could deduce, the ball shape code was based off the equation of a circle.
[2021-10-19] Finished Lab 5. Implemented base siren and modifications to upper and lower tone limits, wailing speed, and the amount of wail instances.
Warning: If you use the pink speaker in Lab 5, make sure it is in the correct mode (wired and not "Bluetooth" mode.) Two other students and I were struggling to get the speaker to work and play the sounds based off of the uploaded code because the speaker was in "Bluetooth" mode. The speaker's light was blinking and on most Bluetooth audio devices, a blinking light means that it is in "Pairing" mode and trying to connect to a device. Click the "M" button on the bottom to set it to "Wired" mode and the light should stop blinking and stay constant. Also beware, the pink speaker is loud and I couldn't figure out how to change the volume while it was connected to the FPGA.
[2021-10-19] Finished Lab 5 and Lab 6. Implemented pong video game with hardware setup below.
Lab 5 Base Siren.MOVVideo of Base Siren Implementation
https://drive.google.com/file/d/1d3FsSVyeedG4PEKa1FUGxRRLOYhf0udq/view?usp=sharing
Lab 6 Hardware Setup
[2021-12-13] All work done from the previous checkpoint on 2021-10-19 until now has been related to the final project. The final project documentation and work explanation can be found in the README.md file on the project GitHub repository below:
github.com/mjaworski22/CPE-487-Final-Project
I have taken home one of the FPGAs (with Professor Lu's permission) for me to use over the winter break. I will try to get better at VHDL and implement deep learning algorithms on the Nexys-A7 board.
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