Digital Systems Design

Vivado does not run on my Mac. Installation required creating a Windows partition on MacOS via Boot-Camp software
Vivado Design Suite was installed successfully on my Windows partition
Textbook Chapters 2-4

Week 3: 7-Segment Decoder Lab Part 1

Chapter 5 & 6
Beginning of Lab 1, 7-Segment Decoder Project

Lab 2: 7-Segment Decoder

Simulation successfully processed within Vivado
Instructions followed from Lab 1 on GitHub

GUI Showing leddec .vhu and .xdc running properly to generate simulation
Syntheses and Implementation functioning properly
Bitrate successfully generated
Flashed to board, switches function

Week 4: 7-Segment Decoder Part 2 and Hex Counter

Chapters 7 & 8
hexcount.vhd and counter.vhd created
hexcount.xdc created
Flashed to board
Hexcounter counts automatically
Completed Lab 2 Four Digit Hex Counter

Lab 2: Four Digit Hex Counter

Programmed Device to count on its own
Generated memory configuration file
Made hex values cycle from memory config file

Week 5: Short Week

Only one class this week due to holiday
Luckily I'm ahead of schedule with Lab 2
Chapter 9

Week 6: Registers and Data Objects

Chapters 10 and 11
Lab 3 using video monitor with board for the first time

Lab 3: Bouncing Ball

Created sources clk_wiz_0, clk_wiz_0_clk_wiz, vga_sync, ball, and vga_top
Created restraint vga_top
Plugged in monitor
Ran Implementation, generated bitstream
Lab successful

Edit as Lab Assistant:

modified ball.vhd to change the size and color of the ball

ball.vhd

constant size: integer:= 20;

...

red <= NOT ball_on;

green <= '1';

blue <= NOT ball_on;

modified ball.vhd to change from a square to a round ball

ball.vhd

BEGIN

IF ((((CONV_INTEGER(pixel_col)-CONV_INTEGER(ball_x))*

(CONV_INTEGER(pixel_col)-CONV_INTEGER(ball_x)))+

((CONV_INTEGER(pixel_row)-CONV_INTEGER(ball_y))*

(CONV_INTEGER(pixel_row)-CONV_INTEGER(ball_y)))) <= (size*size)) THEN

ball_on <= '1';

ELSE

ball_on <= '0';

modified ball.vhd to implement horizontal ball movement using respective x lines of code

ball.vhd

SIGNAL ball_y_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000100";

SIGNAL ball_x_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000100";

...

WAIT UNTIL rising_edge(v_sync);

-- allow for bounce off top or bottom of screen

IF ball_y + size >= 600 THEN

ball_y_motion <= "11111111100"; -- -4 pixels

ELSIF ball_y <= size THEN

ball_y_motion <= "00000000100"; -- +4 pixels

END IF;

IF ball_x + size >= 600 THEN

ball_x_motion <= "11111111100"; -- -4 pixels

ELSIF ball_x <= size THEN

ball_x_motion <= "00000000100"; -- +4 pixels

END IF;

ball_y <= ball_y + ball_y_motion;

ball_x <= ball_x + ball_x_motion;

END PROCESS;

Week 7: No Class

Professor Lu in India
COVID-19 has closed in-person classes until the end of the semester
Classes will be online in the meantime

Week 8: First Online Lecture

Chapter 12 - Looping constructs
Figuring out how class will be structured in continued online lectures
I will attempt to complete labs without the board on-hand

Lab 4: Hex Calculator

Unable to acquire hardware due to COVID-19
Created keypad.vhd, leddec16.vhd, hexcalc.vhd, and hexcalc.xdc
Ran functioning synthesis and implementation

Modified leddec16.vhd to perform leading zero suppression (modifications in bold)

leddec16.vhd

anode <= "1110" when dig="00" and data /= X"0000" else -- digit 0

"1101" when dig="01" and data(15 downto 4) /= X"000" else -- digit 1

"1011" when dig="10" and data(15 downto 8) /= X"00" else -- digit 2

"0111" when dig="11" and data(15 downto 12) /= X"0" else -- digit 3

"1111";

Modified hexcalc.vhd to support subtraction options (modifications in bold)

hexcalc.vhd

entity hexcalc is

Port ( clk_50MHz : in STD_LOGIC;

SEG7_anode : out STD_LOGIC_VECTOR (3 downto 0);

SEG7_seg : out STD_LOGIC_VECTOR (6 downto 0);

bt_clr : in STD_LOGIC;

bt_plus : in STD_LOGIC;

bt_eq : in STD_LOGIC;

KB_col : out STD_LOGIC_VECTOR (4 downto 1);

KB_row : in STD_LOGIC_VECTOR (4 downto 1 );

bt_sub: in STD_LOGIC);

...

signal plus_or_sub: STD_LOGIC;

...

when ENTER_ACC =>

if kp_hit = '1' then

nx_acc <= acc(11 downto 0) & kp_value;

nx_state <= ACC_RELEASE;

elsif bt_plus = '1' then

nx_state <= START_OP;

plus_or_sub <= '1';

elsif bt_sub = '1' then

nx_state <= START_OP;

plus_or_sub <= '0';

else nx_state <= ENTER_ACC;

end if;

...

when ENTER_OP =>

display <= operand;

if (bt_eq = '1' and plus_or_sub = '1' )then

nx_acc <= acc + operand;

nx_state <=SHOW_RESULT

elsif (bt_eq = '1' and plus_or_sub = '0' )then

nx_acc <= acc - operand;

nx_state <= SHOW_RESULT;

elsif kp_hit = '1' then

nx_operand <= operand(11 downto 0) & kp_value;

nx_state <= OP_RELEASE;

else nx_state <= ENTER_OP;

end if;

Edit as Lab Assistant:

Modified port map in the hexcalc.xdc file to include new button

hexcalc.xdc

set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { bt_sub }];

Modified code ran functioning synthesis and implementation

Week 9: Picking up the Pieces

Thinking about how to propose a project without a board
Researching ideas on my own time
Discussion of ways to communicate in class

Lab 5: DAC Siren

Created dac_if.vhd, siren.vhd, siren.xdc, tone.vhd, wail.vhd, and siren.xdc
Ran functioning synthesis and implementation
Modified siren.vhd to designate left and right channels

siren.vhd

entity siren is

Port ( clk_50MHz : in STD_LOGIC; -- system clock (50 MHz)

BTN0 : in STD_LOGIC;

SW0 : IN STD_LOGIC;

SW1 : IN STD_LOGIC;

SW2 : IN STD_LOGIC;

SW3 : IN STD_LOGIC;

SW4 : IN STD_LOGIC;

SW5 : IN STD_LOGIC;

SW6 : IN STD_LOGIC;

SW7 : IN STD_LOGIC;

...

lo_clk <= tcount(19); -- clock to control wailing of tone (47.6 Hz)

wail_speed(0) <= SW0;

wail_speed(1) <= SW1;

wail_speed(2) <= SW2;

wail_speed(3) <= SW3;

wail_speed(4) <= SW4;

wail_speed(5) <= SW5;

wail_speed(6) <= SW6;

wail_speed(7) <= SW7;

...

w1: wail port map( lo_pitch => lo_tone, -- instantiate wailing siren

hi_pitch => hi_tone,

wspeed => wail_speed,

wclk => slo_clk,

button_press => BTN0,

audio_clk => audio_clk,

audio_data => data_L);

w2: wail port map( lo_pitch => hi_tone, -- instantiate wailing siren

hi_pitch => lo_tone,

wspeed => wail_speed,

wclk => slo_clk,

button_press => BTN0,

audio_clk => audio_clk,

audio_data => data_R);

--data_R <= data_L; -- commenting this part out

end Behavioral;

modified wail.vhd to support changes

wail.vhd

component tone is

Port ( clk : in STD_LOGIC;

pitch : in UNSIGNED (13 downto 0);

btn_press : in STD_LOGIC;

data : out SIGNED (15 downto 0));

end component;

...

tgen: tone port map(clk => audio_clk, -- instance a tone module

btn_press => button_press,

pitch => curr_pitch, -- use curr-pitch to modulate tone

data => audio_data);

end Behavioral;

Modified tone.vhd to add input buttons for square waves

tone.vhd

entity tone is

Port ( clk : in STD_LOGIC; -- 48.8 kHz audio sampling clock

pitch : in UNSIGNED (13 downto 0); -- frequency (in units of 0.745 Hz)

btn_press : in STD_LOGIC;

data : out SIGNED (15 downto 0)); -- signed triangle wave out

end tone;

...

signal index: signed (15 downto 0); -- index into current quadrant

signal data_sq:SIGNED(15 downto 0);

signal data_tri:SIGNED(15 downto 0);

...

with quad select

data_sq <= to_signed(16383,16) when "00",

to_signed(-16383,16) when "01",

to_signed(16383,16) when "10",

to_signed(-16383,16) when others;

with quad select

data_tri <= index when "00",

16383 - index when "01",

0 - index when "10",

index - 16383 when others;

--with quad select

--data <= index when "00", -- 1st quadrant

--16383 - index when "01", -- 2nd quadrant

--0 - index when "10", -- 3rd quadrant

--index - 16383 when others; -- 4th quadrant

tone_select: process

begin

if btn_press = '1' then

data <= data_sq;

else

data <= data_tri;

end if;

end process;

end Behavioral;

Modified code ran functioning synthesis

Similarly to Lab 4, I need to experiment with physical board which I do not have access to. This is as far as the lab can be completed virtually.

Edit as Lab Assistant:

Changed siren.xdc file to make pins function

siren.xdc

set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTN0 }]; #IO_L9P_T1_DQS_14 Sch=btnc

set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW0 }]; #IO_L24N_T3_RS0_15 Sch=sw[0]

set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW1 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW2 }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]

set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW3 }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]

set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW4 }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]

set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW5 }]; #IO_L7N_T1_D10_14 Sch=sw[5]

set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW6 }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]

set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW7 }]; #IO_L5N_T0_D07_14 Sch=sw[7]

Was able to correct and properly implement this code with its modifications

Week 10: Last Lab

Continuing considerations for final project somehow using hardware in my house:
- 3D Printing
- HAM Radio
- VR Headset
Suggestions from others involve:
- GRASS: GRAph Spectral Sparsifier
- LabVIEW
- MATLAB

Lab 6: PONG

Created clk_wiz.vhd_0, clk_wiz_0_clk_wiz.vhd, vga_sync.vhd, bat_n_ball.vhd, adc_if.vhd, pong.vhd, and pong.xdc
Ran functioning synthesis and implementation
Modified pong.vhd to allow changing ball speed

Similarly to Lab 4 and 5, I need to experiment with physical board which I do not have access to. This is as far as the lab can be completed virtually.

Edit as Lab Assistant:

Kevin Lu provided assistance integrating my modified code and getting it to function. The modifications to the original files are documented below:
Modified bat_and_ball.vhd

bat_and_ball.vhd

ENTITY bat_n_ball IS

PORT (

v_sync : IN STD_LOGIC;

pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0);

pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0);

bat_x : IN STD_LOGIC_VECTOR (10 DOWNTO 0); -- current bat x position

serve : IN STD_LOGIC; -- initiates serve

red : OUT STD_LOGIC;

green : OUT STD_LOGIC;

blue : OUT STD_LOGIC;

SW : IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- ball speed

hits: OUT STD_LOGIC_VECTOR (15 DOWNTO 0) -- count the number of successful hits

);

END bat_n_ball;

...

SIGNAL ball_x_motion, ball_y_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := ball_speed;

SIGNAL hitcount : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL stop_dbl_hit : STD_LOGIC; -- stops the counter from registering 2 hits at once

...

mball : PROCESS

VARIABLE temp : STD_LOGIC_VECTOR (11 DOWNTO 0);

BEGIN

ball_speed <= (10 DOWNTO SW'length => '0') & SW;

WAIT UNTIL rising_edge(v_sync);

IF serve = '1' AND game_on = '0' THEN -- test for new serve

game_on <= '1';

ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels

ball_x_motion <= ball_speed + 1;

bat_w <= 40;

hitcount <= CONV_STD_LOGIC_VECTOR(0, 16);

stop_dbl_hit <= '0';

ELSIF ball_y <= bsize THEN -- bounce off top wall

ball_y_motion <= ball_speed; -- set vspeed to (+ ball_speed) pixels

stop_dbl_hit <= '0';

ELSIF ball_y + bsize >= 600 THEN -- if ball meets bottom wall

ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels

game_on <= '0'; -- and make ball disappear

END IF;

...

IF (ball_x + bsize/2) >= (bat_x - bat_w) AND

(ball_x - bsize/2) <= (bat_x + bat_w) AND

(ball_y + bsize/2) >= (bat_y - bat_h) AND

(ball_y - bsize/2) <= (bat_y + bat_h) AND

stop_dbl_hit = '0' THEN

ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels

bat_w <= bat_w - 1;

hitcount <= hitcount + 1;

hits <= hitcount;

stop_dbl_hit <= '1';

END IF;

modified pong.vhd

pong.vhd

ENTITY pong IS

PORT (

clk_in : IN STD_LOGIC; -- system clock

VGA_red : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- VGA outputs

VGA_green : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

VGA_blue : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

VGA_hsync : OUT STD_LOGIC;

VGA_vsync : OUT STD_LOGIC;

ADC_CS : OUT STD_LOGIC; -- ADC signals

ADC_SCLK : OUT STD_LOGIC;

ADC_SDATA1 : IN STD_LOGIC;

ADC_SDATA2 : IN STD_LOGIC;

btn0 : IN STD_LOGIC; -- button to initiate serve

SW : IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- ball speed

SEG7_anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- anodes of four 7-seg displays

SEG7_seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) -- common segments of 7-seg displays

);

END pong;

...

RCHITECTURE Behavioral OF pong IS

SIGNAL pxl_clk : STD_LOGIC := '0'; -- 25 MHz clock to VGA sync module

-- internal signals to connect modules

SIGNAL S_red, S_green, S_blue : STD_LOGIC; --_VECTOR (3 DOWNTO 0);

SIGNAL S_vsync : STD_LOGIC;

SIGNAL S_pixel_row, S_pixel_col : STD_LOGIC_VECTOR (10 DOWNTO 0);

SIGNAL batpos : STD_LOGIC_VECTOR (10 DOWNTO 0); -- 9 downto 0

SIGNAL serial_clk, sample_clk : STD_LOGIC;

SIGNAL adout : STD_LOGIC_VECTOR (11 DOWNTO 0);

SIGNAL count : STD_LOGIC_VECTOR (9 DOWNTO 0); -- counter to generate ADC clocks

SIGNAL display : std_logic_vector (15 DOWNTO 0); -- value to be displayed

SIGNAL led_mpx : STD_LOGIC_VECTOR (1 DOWNTO 0); -- 7-seg multiplexing clock

SIGNAL cnt : std_logic_vector(20 DOWNTO 0); -- counter to generate timing signals

COMPONENT adc_if IS

...

COMPONENT bat_n_ball IS

PORT (

v_sync : IN STD_LOGIC;

pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0);

pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0);

bat_x : IN STD_LOGIC_VECTOR (10 DOWNTO 0);

serve : IN STD_LOGIC;

red : OUT STD_LOGIC;

green : OUT STD_LOGIC;

blue : OUT STD_LOGIC;

SW : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

hits : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END COMPONENT;

...

COMPONENT clk_wiz_0 is

PORT (

clk_in1 : in std_logic;

clk_out1 : out std_logic

);

END COMPONENT;

COMPONENT leddec16 IS

PORT (

dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)

);

END COMPONENT;

...

BEGIN

WAIT UNTIL rising_edge(clk_in);

count <= count + 1; -- counter to generate ADC timing signals

END PROCESS;

led_mpx <= cnt(18 DOWNTO 17); -- 7-seg multiplexing clock

serial_clk <= NOT count(4); -- 1.5 MHz serial clock for ADC

ADC_SCLK <= serial_clk;

...

add_bb : bat_n_ball

PORT MAP(--instantiate bat and ball component

v_sync => S_vsync,

pixel_row => S_pixel_row,

pixel_col => S_pixel_col,

bat_x => batpos,

serve => btn0,

red => S_red,

green => S_green,

blue => S_blue,

SW => SW,

hits => display

);

...

clk_wiz_0_inst : clk_wiz_0

port map (

clk_in1 => clk_in,

clk_out1 => pxl_clk

);

led1 : leddec16

PORT MAP(

dig => led_mpx, data => display,

anode => SEG7_anode, seg => SEG7_seg

);

END Behavioral;

modified pong.xdc

pong.xdc

set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L9P_T1_DQS_14 Sch=btnc

set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]

set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]

set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]

set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]

set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[0]}]

set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[1]}]

set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[2]}]

set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[3]}]

set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[4]}]

set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[5]}]

set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[6]}]

set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[0]}]

set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[1]}]

set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[2]}]

set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[3]}]

Took and modified leddec16.vhd from Lab 4 to drive display

leddec16.vhd

-- Turn on anode of 7-segment display addressed by 2-bit digit selector dig

anode <= "1110" WHEN dig = "00" and data /= X"0000" ELSE -- digit 0

"1101" WHEN dig = "01" and data(15 downto 4) /= X"000" ELSE -- digit 1

"1011" WHEN dig = "10" and data(15 downto 8) /= X"00" ELSE -- digit 2

"0111" WHEN dig = "11" and data(15 downto 12) /= X"0" ELSE -- digit 3

"1111";

END Behavioral;

On the official lab page, you can find a video of the modified files running. My video only shows only some of the modifications compared to the latest version
Code modifications on this site and my GitHub is fully up to date

Side Project: 3D Printed Face Mask

See all details of this project here

Week 11 & 12 Final Project: Oscilloscope Music

Without access to a board or any labs, I am forced to get resourceful for this final project. To come up with an idea, I thought to myself, "What objects around my house could contain an FPGA?". After some research, I discovered there are very few mass-produced electronics that contain FPGAs. After more research I discovered test equipment, such as Oscilloscopes, can contain FPGAs. At my previous internship, I acquired an old Tektronix 5403 Oscilloscope from 1974. I understand that this scope does not have an FPGA inside of it, but I am doing my best to work with what I have access to in the trying times of COVID-19. I will conduct my final project using this Oscilloscope.

Oscilloscope music has been a hobby amongst a small community of oscilloscope users. It involves utilizing dual channel audio to "draw" images on an oscilloscope. This is done by running the left and right audio channels to two separate probes while the scope is operating in an XY mode. XY mode renders the voltage (x) in relationship to a second voltage (y) as opposed to a voltage (x) over time (t). The key to rendering images clearly is to keep the two signals in phase with each-other.
Here is a link to Oscilloscope Music, a musician who works on synthesizing audio for this sole purpose. There are albums that can be purchased as well as tutorials on how this can be done at home. In my opinion, the coolest video they have created was the kickstarter proof on concept video, which has the most variation in the drawings. This is the video I want to render on my own scope.

Next, I wanted to utilize the most accessible way I can probe dual channel audio in my home. I don't want to ruin any cables in my house and I don't want to purchase any adapters, so I decided I will probe an aux cord directly.
I looked up the guide for a 3.5 mm audio cord and attached the oscilloscope probes accordingly. I plugged the cord directly into my computer headphone jack.

To figure out how to operate a scope this old, I had to dig and find the user manual for the scope itself, as well as the components in the individual bays. I have attached those below.

tek_5a48.pdf

tek_d40.pdf

tek_5b42.pdf

I also discovered someone on vintagecomputer.net who has done something similar. His guide here was incredibly helpful in understanding how to operate my scope.
Where he has a 5B31 component in his right bay, I have a 5B42. I am referring to the manuals to discover the differences between these components.
I have difficulty setting parameters on my scope, as some dials and switches are broken, I will still continue forward unless I discover something that makes the scope inoperable
- I plug the left audio probe into the 5A48 in the left bay and set it to display channel 1 at 1 Volt/division
- I plug the right audio probe into the 5B42 in the right bay and set the dial to AMPL mode on auto trigger
- I adjust the dials to center the waveform on screen
- Success! The image is slightly more squished than I would like. This is most likely due to the age of the scope or noise from probing the aux cord

To tie things back to Digital System Design, an FPGA could be used to control the audio input into this scope. This could make for an easier method of synthesis without utilizing expensive audio equipment. Over the course of this week I will be looking into using VHDL or Verilog to create a digital two channel audio synthesizer on the FPGA board that could be used as an input to the oscilloscope.

After farther research, I discovered a Nexys A7-100T DMA Audio Test here. This can be used as an audio driver from the current board in this course. The link contains set-up instructions as well as all necessary files.
The program currently is written in Verilog, not VHDL. It supports WAV files, which are the file type used by Oscilloscope music for the highest quality output.
I downloaded this project to Vivado an ran synthesis and it succeeded

For implementation with my Oscilloscope, I would run an AUX cable out of the Nexys A7-100T and probe the cord as shown above. With this setup, I can send WAV files to the Nexys board and display them on the Oscilliscope directly from the AUX port.
Without the physical board, this is as far as I can take this final project. When this quarantine is over, perhaps I can use one of the school's Nexys boards to implement this project.

Week 13: Contributions Simulation Mode Experiments

At the professors request, I decided to run the simulation of the Nexys A7-100T DMA Audio Test program to experiment with the feature
I clicked "run simulation" and ran a behavioral simulation. The result is shown below
All of the variables for this complex multi-purpose program can be seen from 0 to 1000 ns

After some research, I discovered that Verilog is the only language to support post-synthesis timing simulations, I decided I would try this to see if I can get it working.
I clicked "run post synthesis timing simulation" and the image to the right was shown
The function runs but gets stuck on "executing elaborate step"

To try and simplify this process for my understanding, I decided to run a behavioral simulation of Lab 1 an image of this can be seen
With less variables, this simulation is much easier to understand.
The four set values: digit (U) , data (U) , anode (f) , seg (7f) can be seen from 0 to 1000 ns
I would assume that "seg" is the values of the segmented display and 7f is Hex
This simulation can be an easy way to troubleshoot a program and can help users understand exactly which data is being sent through the board

Weeks Following Fall 2020: Appointed as Lab Assistant

I have been appointed as a Grader and Lab Assistant for this class by Kevin Lu
I was given a Nexys A7 100T and required lab hardware to take home
I will spend the semester of Fall 2020 completing the labs I could not finish from Spring 2020
Edits to each lab will be listed throughout this page under the heading "Edit as Lab Assistant"
As of 9/11/2020 I have completed updating all the labs

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