Lab 1: Seven Segment Decoder

Objectives:

• The purpose of this lab is to introduce you to the NEXYS2 FPGA development board and a software environment that will allow you to design a hardware system in VHDL, synthesize your design to create an FPGA configuration file, download the configuration file on to an FPGA and then run the configured FPGA to achieve the desired hardware functionality.

Hardware:

The group will be using NEXYS 4 DDR, and the information is shown below:

Important Links for Lab 1

Vivado 2018.3 Download: Link to Xilinx site for installer

Lab procedures can be found at Prof. Ackland's site: Link to Ackland's Lab 1

Steps for adding Nexys4 DDR into Vivado: Link to Digilent Instructions

Steps for programming the Nexys4 DDR in Vivado: Link to Digilent Instructions

XDC Constraint File courtesy of group 4 from Fall 2018: Link to Github Link to their Website

Import Nexys4 DDR board files to Vivado from the download link above

Download the XDC file from the github above and comment in the appropriate lines of code, as well as rename the variables to match the variables in the VHDL file you download from Prof. Ackland's Lab 1 instructions

Follow the step by step instructions for Nexys4 DDR programming from the Digilent site to ensure smooth compilation

Step by Step instructions for Lab 1

First and foremost, you will need to go to Xilinx site and download the most recent edition of Vivado (We used Vivado 2018.3, 64-bit edition). There are additional steps required here such as creating a student account with Xilinx and verifying your email, however once you complete those steps you will be able to download the installer for Vivado.

Once Vivado is installed, you will want to add the Nexys4 DDR board to the Vivado Suite. The instructions can be found here. From this link you will be download a zip folder containing several Digilent boards, including the Nexys4 DDR. After unzipping the folder, you will need to copy the new board files into the Vivado directory labeled "board_files", located in C:\Xilinx\Vivado\2018.3\data\boards\board_files . Reminder, Vivado may not be in the C: drive, it depends on where you initially installed it. Once you copy the new board files into the Vivado directory, restart Vivado and you will now be able to choose the Nexys4 DDR board during setup.

Once you have the new board files in the appropriate directory, you will want to follow the steps on the Digilent site to program the Nexys4 DDR, found here.

Important notes:

• Step 1.4, you will want to add the VHDL file found on page 7 of Prof. Ackland's Lab 1 instructions (Link). The easiest way to do this is on the Add sources page, click the "Create File" button, setup the file type to VHDL, and set the file name to "leddec"; no need to add the file type (.vhdl) at the end. Then click okay, once you get through all the parts of section 1, you will be able to navigate to your new leddec.vhd file in the Sources window (you may need to expand the Design Sources folder to see it). Double click on the file, and copy and paste the code from the Lab instructions over any code in the VHDL file and save.
• Step 1.6, you will want to add the constraint file found at the github here. The constraint file has everything commented out, you will need to "comment in" the corresponding definitions, and rename them, for the VHDL file to respond properly.

• Follow step 3, Programming with JTAG, to program the Nexys4 with the microusb cable in Vivado.