2021-02-04 Created and published a Google Site with a link to my GitHub repository and a section for weekly reports; downloaded the the textbook Free Range VHDL and read over chapters 1-3; studied the IEEE Editorial Style Manual

2021-02-11 Read up to Chapter 7 in the Free Range VHDL Manual

2021-02-25 Could not pick up an FPGA today but will reach out to Professor Lu to pick up the FPGA next Tuesday. Looked over Lab 1 and followed along to Professor Lu when demonstrating the lab

2021-03-04 - Picked up the FPGA from Professor Lu Tuesday afternoon and completed part 1 of Lab 1 with group members Cooper Garren and Robert Roettger during class

2021-03-11 - Worked with my group to catch up on labs. Completed Lab 2 Monday evening before the next class and successfully

2021-03-18 - Began working on Lab 3: Bouncing Ball. Successfully ran the lab and adjusted the size of the ball and x-position speed

2021-03-25 - Brainstormed ideas for the final project. Two possible ideas are a Dance Dance Revolution based game and a number

2021-04-8 - Further talked with my group about the final project and began working on Lab 4 and 5.

2021-04-15 - Finished Lab 6 with group and began reading code from Random Six Digit Hex Number Generator to use for the Nexys A7 board.

2021-04-22 Continued analyzing code from the Intel board project from last year but receiving errors in Vivado and having issues creating the XDC file.

2021-04-29 - Using code from the Intel board project proved to be more difficult than previously thought. Trying to figure how to properly map the ports in the XDC file.

2021-05-06 - Switched names of the XDC and leddec files for consistency with the top file and with the code in the "leddec" file which is now seg7_lut. Changes to these files can be found in the GitHub repo here.

Project website link: https://sites.google.com/stevens.edu/cpe487-s2021-rng/project-overview