Research Interests

Deep Neural Network Accelerator Design

• In-memory-computing for data-centric neural network accelerator

• Approximate computing techniques for low power consumption

• Zero-aware (Sparsity-based) hardware architecture (zero weight from pruning, zero input from ReLU-inference)

• Various implementation techniques based on domain change

Digital Signal Processors

• Post Quantum Cryptography (ML-KEM, ML-DSA) Hardware Accelerator Design

• Efficient interface design of embedded memory for low power image processing (MPEG/H.264) applications

• Memory based computation of cryptography processor and physical unclonable function (PUF)

Advanced SoC Design Methology

• Stochastic computing-based approximation and hardware optimization

• Asynchronous Circuit Design Method for Resolving Pipeline Imbalance and Side-Channel Analysis Resistance

• Development of a new standard cell for hardware implementation optimization

Embedded Memory Design

• Emerging memory (STT-MRAM, SOT-MRAM, Domain-Wall Memory) design

• Memory (SRAM/eDRAM/CAM) customization in application-specific purpose

• Memory yield estimation modeling