實驗室論文發表

Xin-Yu Shih, You-Chen Li, Geng-Hong Li, and Jia-Han Xie, “High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding with Reconfigurable Pipelined Sorter and SCF-Decoding with Non-Uniform 4-Segment CRC,” in IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 4, pp. 2349-2353, April 2024 (SCI, EI). 

 Xin-Yu Shih, Hsiang-En Wu, and Ming-Xian Cai, “Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications,” in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 12, pp. 5302-5315, Dec. 2023 (SCI, EI). 

Xin-Yu Shih, Chen-Yen Song, and Yao-Yu Lu, “Unified Chip Hardware Architecture of KD-Tree Mean-Based Trainer and Speeding-Up Classifier with Repeat-Point Searching for Various Applications,” in Integration, the VLSI Journal, 93 (2023), 102056, Nov. 2023 (SCI, EI).

Xin-Yu Shih, Yao Chiu, and Hsiang-En Wu, “Design and Implementation of Decision-Tree (DT) Online Training Hardware using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 2, pp. 759-771, Feb. 2023 (SCI,EI).

Xin-Yu Shih, Jui-Hung Tsai, Bing-Xuan Li, and Chi-Ping Huang, “Reconfigurable Hardware Architecture of Area-Efficient Multi-Mode Successive Cancellation (SC) Decoder,” IEEE Transactions on Circuits and Systems—II: Express Briefs (TCAS-II), vol. 69, no. 4, pp. 2291-2295, April 2022 (SCI, EI).

Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu, “Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture with Changeable-Radix Processing Elements,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 65, no. 11, pp. 3942-3955, Nov. 2018 (SCI, EI).

Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu, “VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix Based FFT Hardware Architecture for 3GPP-LTE Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 65, no. 1, pp. 118-129, Jan. 2018 (SCI, EI).

Xin-Yu Shih, Yue-Qu Liu, and Hong-Ru Chou, “48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 64, no. 6, pp. 1456-1467, Jun. 2017 (SCI, EI).

Xin-Yu Shih and Hong-Ru Chou, “Flexible Design and Implementation of QC-Based LDPC Decoder Architecture for On-Line User-Defined Matrix Downloading and Efficient Decoding,” Integration, the VLSI Journal, 64 (2019), pp. 40-49, Jan. 2019 (SCI, EI).

Xin-Yu Shih, Po-Chun Huang, and Hong-Ru Chou, “VLSI Design and Implementation of a Reconfigurable Hardware-Friendly Polar Encoder Architecture for Emerging High-Speed 5G System,” Integration, the VLSI Journal, 62 (2018), pp. 292-300, Jun. 2018 (SCI, EI).

Xin-Yu Shih, Lok Hin Samuel Leung, and Geng-Hong Li (2023, July), “Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2023), Pingtung, Taiwan, 17-19, July, 2023.

Xin-Yu Shih, Rou-Jyun Chen, and Zhen-Yi Lu (2022, Oct), “Performance-Improved AdaBoost with Parameterized and Simple-Operation Genetic Algorithm,” in Proc. IET International Conference on Engineering Technologies and Applications (IET ICETA 2022), Changhua, Taiwan, 14-16, October, 2022. 

Xin-Yu Shih and Yao-Yu Lu (2022, Aug), “Systematic and Flexible Genetic-Algorithm-Based Feature Reduction for Decision Tree ML-Validation,” in Proc. 2022 IET International Conference on Engineering Technologies and Applications (IET ICETA 2022), Changhua, Taiwan, 14-16, October, 2022. 

Xin-Yu Shih and Geng-Hong Li (2022, Aug), “VLSI Architecture of Low-Cost High-Order Matched Filter Using 8-Phase Switching Paths for Undersea Object-Identification Applications,” in Proc. 2022 IET International Conference on Engineering Technologies and Applications (IET ICETA 2022), Changhua, Taiwan, 14-16, October, 2022. 

Xin-Yu Shih and Chen-Yen Song (2022, July), “Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2022), Taipei, Taiwan, 06-08 July, 2022. 

Xin-Yu Shih, Ming-Jyun Wu, and Hsiang-En Wu (2022, April) “A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2022), Taipei, Taiwan, 06-08 July, 2022. 

Xin-Yu Shih and Hsiang-En Wu (2022, April), “Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2022), Taipei, Taiwan, 06-08 July, 2022. 

Xin-Yu Shih and Hsiang-En Wu (2022, April), “Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2022), Taipei, Taiwan, 06-08 July, 2022. 

Xin-Yu Shih (2019, Nov), “VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure,” in Proc. 2019 6th International Conference on Systems and Informatics (ICSAI 2019), Shanghai, China, 2-4 November, 2019.

Xin-Yu Shih (2019, Aug), “Ultra-Low-Cost VLSI Circuit of Main Computing Kernel Engine for Future Deep Learning AI-Applications,” in Proc. 2019 International Conference on Engineering and Applied Science (ICEAS), Hawaii, USA, 6-8 August, 2019.

Xin-Yu Shih (2019, Jun), “Hardware-Friendly Circuit of Core Sorter Computing Engine for Successive Cancellation List (SCL) Polar Decoders,” in Proc. 2019 Asia Conference on Engineering and Information (ACEAI), Beijing, China, 18-21 June, 2019.

Xin-Yu Shih (2019, May), “Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications,” in Proc.  IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2019), Jiaosi, Taiwan, 20-22 May, 2019.

Xin-Yu Shih (2018, Dec), “Design and Analysis of 5-Step High-Efficient Early Termination Approach for LDPC Layered Decoding in Advanced Communication Worlds,” in Proc. 2018 Asia-Pacific Conference on Engineering and Applied Sciences (APCEAS), Sydney, Australia, 18-20 December, 2018.

Xin-Yu Shih (2018, Aug), “Innovative Hardware Architecture of High-Performance LDPC Decoder Design with Real-Time QC-LDPC Matrix Programming,” in Proc. 2018 International Research Symposium on Engineering and Technology (2018 IRSET), Singapore, 28-30 August, 2018.

Xin-Yu Shih (2018, Jul), “Design and Analysis of Reduced-Operation Based 7x7 Median Filter with Innovative 4-Phase Quick Searching Approach,” in Proc. 2018 Global Conference on Engineering and Applied Science (2018 GCEAS), Tokyo, Japan, 10-12 July, 2018.

Xin-Yu Shih (2018, Jul), “Reconfigurable VLSI Architecture of Different-Radix Based Polar Encoder Chip with Well-Arranged 2D-FIFO Planning,” in Proc. 2018 Global Conference on Engineering and Applied Science (2018 GCEAS), Tokyo, Japan, 10-12 July, 2018.

Xin-Yu Shih and Yue-Qu Liu (2018, May), “A Novel VLSI Architecture of Low-Area-Cost FIR-Based Matched Filter Hardware Design for Under-Water Applications,” in Proc. 8th International Congress on Engineering and Information (2018 ICEAI), Sapporo, Japan, 1-3 May, 2018.

Xin-Yu Shih, Po-Chun Huang, and Kai Lin (2018, May), “VLSI Architecture of Super-High-Throughput and High-Speed K-Parallel Polar Encoder Designs for Emerging 5G Communication Applications,” in Proc. 8th International Congress on Engineering and Information (2018 ICEAI), Sapporo, Japan, 1-3 May, 2018.

Xin-Yu Shih, Hong-Ru Chou, and Jun-Jiang Chen (2018, May), “A Well-Arranged FIFO-Storage Distribution Design Plan for Fully Supporting 50 Different FFT Sizes in 3GPP-LTE Communication Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2018), Taichung, Taiwan, 19-21 May, 2018.

Xin-Yu Shih, Hong-Ru Chou, and Hsin-Hsien Lin (2018, May), “Area and Speed Optimization of a 5x5 Median Filter Design with 3-Direction Fast Searching Approach for Image Signal Processing Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2018), Taichung, Taiwan, 19-21 May, 2018.

Xin-Yu Shih, Yue-Qu Liu, and Yi-Ti Cheng (2018, May), “Area-Efficient VLSI Architecture of High-Order Matched Filter Design Using Odd-and-Even Phase Processing for Image Recognition Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2018), Taichung, Taiwan, 19-21 May, 2018.

Xin-Yu Shih and Hong-Ru Chou (2018, Jan), “Low-Cost and High-Speed VLSI Hardware Architecture of Discrete Pascal Transform for Signal and Image Processing Applications,” in Proc. 2018 Hong Kong International Conference on Engineering and Applied Sciences, Hong Kong, China, 24-26 January, 2018.

Xin-Yu Shih and Yue-Qu Liu (2018, Jan), “An Innovative Hardware Design of FFT Reconfigurable Computing Kernel Engine with 6 Changeable-Radix Modes for 3GPP LTE Applications,” in Proc. 2018 Hong Kong International Conference on Engineering and Applied Sciences, Hong Kong, China, 24-26 January, 2018.

Xin-Yu Shih and Hong-Ru Chou (2017, Dec), “Design and Analysis of Reconfigurable FFT Computing Kernel with 20 Combined-Radix Modes for 3GPP-LTE Communication Systems,” in Proc. 5th Seoul International Conference on Applied Science and Engineering (2017 SICASE), Seoul, Korea, 5-7 December, 2017.

Xin-Yu Shih (2017, Dec), “XYZ-Direction Fast Minimum Searching Approach of High-Row-Weight LDPC Decoders for Advanced Communication Applications,” in Proc. 5th Seoul International Conference on Applied Science and Engineering (2017 SICASE), Seoul, Korea, 5-7 December, 2017.

Xin-Yu Shih and Hong-Ru Chou (2017, Oct), “A 2-D Grouping FIFO Based Hardware Architecture for Supporting 36-Mode Hybrid-Radix FFT Design in 3GPP-LTE Systems,” in Proc.  2017 IEEE 6th Global Conference on Consumer Electronics (IEEE GCCE 2017), Nagoya, Japan, 24-27 October, 2017.

Xin-Yu Shih and Yue-Qu Liu (2017, Oct), “Cost-Efficient Hardware Design of Coarse and Fine Rotation Based FFT Twiddle Factor Generator for 3GPP LTE Applications,” in Proc. 2017 IEEE 6th Global Conference on Consumer Electronics (IEEE GCCE 2017), Nagoya, Japan, 24-27 October, 2017.

Xin-Yu Shih and Yu-Chun Chen (2017, Jun), “2-Dimensional Minimum Fast-Searching Design Approach of LDPC Decoder Architecture for IEEE 802.11n/ac/ax Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2017), Taipei, Taiwan, 12-14 June, 2017

Xin-Yu Shih and Po-Chun Huang (2017, Jun), “VLSI Design of An Ultra-High-Speed Polar Encoder Architecture Using 16-Parallel Radix-2 Processing Engines for Next-Generation 5G Applications,” in Proc. IEEE International Conference on Consumer Electronics - Taiwan (IEEE ICCE-TW 2017), Taipei, Taiwan, 12-14 June, 2017.

Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu (2017, Feb), “A Low-Area Fully-Reconfigurable Hardware Design of FFT System for 3GPP-LTE Standard,” in Proc. 2017 19th International Conference on Computational Intelligence, Communication and Signal Processing, Paris, France, 23-24 February, 2017.

Xin-Yu Shih and Hong-Ru Chou (2017, Jan), “Reconfigurable Hardware Design of Low-Area-Cost Computing Kernel Engine for Different Radixes of Single-Path Delay Feedback FFT Systems,” in Proc. 2017 IEEE International Conference on Consumer Electronics (IEEE ICCE 2017), Las Vegas, USA, 8-10 January, 2017.

Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu (2016, Oct), “Reconfigurable VLSI Design of Processing Kernel for Multiple-Radix Single-Path Delay Feedback FFT Systems,” in Proc. 5th IEEE Global Conference on Consumer Electronics (IEEE GCCE 2016), Kyoto, Japan, 11-14 October, 2016.

Xin-Yu Shih, Po-Chun Huang, and Yu-Chun Chen (2016, Oct), “High-Speed Low-Area-Cost VLSI Design of Polar Codes Encoder Architecture Using Radix-k Processing Engines,” in Proc.  5th IEEE Global Conference on Consumer Electronics (IEEE GCCE 2016), Kyoto, Japan, 11-14 October, 2016.