聯發科
邱堯
具低延遲且高速率的決策樹訓練器和分類器之硬體架構設計與實現
Design and Implementation of Decision-Tree Training and Classifying Hardware Architecture with Featuring Low Latency and High Speed
瑞昱
周宏儒
適用於3GPP-LTE通訊系統的組合基底式快速傅立葉轉換器之可重置架構設計與實現
Design and Implementation of Reconfigurable Combined-radix FFT Architecture for 3GPP-LTE Communication Applications
李秉軒
雙模式連續消除及連續消除列表極化碼解碼器之可重置式架構設計與實現
Reconfigurable Design and Implementation of Dual-mode Successive Cancellation and Successive Cancellation List Polar-Decoder Hardware
宋承諺
平均數基底的訓練器與重複點序列的加速分類器之K維樹硬體架構設計
Hardware Architecture of KD-Tree Mean-Based Trainer and Speeding-Up Classifier with Repeated-Point Sequence
聯詠
呂曜宇
應用於硬體木馬偵測的機率累加式閘級特徵萃取之軟硬體協作設計
Software and Hardware Co-Design of Probability-Accumulated Gate-Level Feature Extraction for Hardware Trojans Detection
張瑋倫
具低面積成本的自適應高可靠連續消除列表解碼器之晶片架構設計
Low-Cost Chip Architecture of Adaptive and High-Reliability Successive Cancellation List (SCL) Decoder
群聯
黃品諭
應用於硬體木馬偵測之高相容性且快速閘級特徵萃取硬體設計與實作
Design and Implementation of High-Speed Gate-Level Feature Extraction Chip with High Compatibility for Hardware Trojans Detection Applications
高通
梁樂軒
具雙層計算單元和多位元解碼的多模式連續消除列表解碼器之硬體架構設計
Hardware Architecture of Multi-mode Successive Cancellation List (SCL) Decoder with Double-column Processing Element and Multi-bit Decision Decoding
達發科
謝佳翰
具減少延遲特色的連續消除列表解碼器之可重置式晶片架構設計與實作
Design and Implementation of Latency-Reduced Reconfigurable Hardware Chip Architecture of Successive Cancellation List (SCL) Decoder
吳祥恩
適用於人類疾病偵測應用的雙模式支持向量機訓練器和分類器之晶片架構設計
Chip Architecture of Dual-Mode Support Vector Machine(SVM) Trainer and Classifier Hardware for Human Disease Detection Applications
蔡明憲
用於輔助網路安全異常偵測的快速訓練和可支援多分類之集成式學習晶片設計與實現
Design and Implementation of Fast Trainer and Multi-label-supported Classifier for Ensemble Learning Chip for assisting anomaly detection in Cybersecurity
譜瑞
李耕宏
機器學習輔助式自動選擇模式的自適應多模式極化碼解碼器之晶片設計與實現
Design and Implementation of Machine-Learning-Aided Auto-Mode-Selection Polar Decoder Chip Featuring Adaptive Multiple Modes
創意電子
黃柏鈞
適用於下一世代通訊系統的高效能極性編碼器之設計與實現
Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems
原相
李佑辰
可支援雙演算法且多模式的高面積效率極化碼解碼器之晶片架構設計
High-Hardware-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL with Reconfigurable Pipelined Sorter and SCF with Non-Uniform 4-Segment CRC
義隆電子
蔡睿紘
可支援多模式的高效能連續消除解碼器之可重置式硬體架構設計
Reconfigurable Hardware Architecture of High-Performance Successive Cancellation (SC) Decoder with Supporting Multiple Modes
黃繼平
可組建式且可重置式的多模式連續消除極化碼解碼器之硬體架構設計與實作
Design and Implementation of Combined-Type and Reconfigurable Successive Cancellation Polar-Decoder Architecture with Multi-Mode Usage
陳璽丞
可偵測資訊安全威脅的樹架構式 K 平均分群訓練器和分類器之通用型晶片架構設計
Unified Chip Architecture of Tree-Structure-Based K-Means Clustering Trainer and Classifier for Detecting Information Security Threats
敦泰電子
劉岳衢
具模組化建構的快速傅立葉轉換器之可重置硬體設計與實現
Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture