Low Switching Noise Parallel Interface Circuit System

摘要

單端式平行鍵結系統的資料速率通常會受限於介面電路系統自身所產生的同步切換雜訊與耦合雜訊。為了同時降低這兩種雜訊以提升資料速率，本論文實現了循序驅動的電路技巧來應用於平行鍵結系統的介面電路上。讓所有的介面電路一個接一個地在不同時間點進行資料的傳送，讓所消耗的動態電流平均地分配在不同時間，使電源供應端的電流變化量大幅減少，而得到較低的同步切換雜訊。 

雜訊抑制介面電路系統包含了數位式的延遲鎖定迴路、轉態偵測電路、複製驅動電路與切換式電壓調變電路，以及輸出驅動電路。延遲鎖定迴路是為了產生多相位的參考時脈，讓介面電路在不同時間驅動，轉態偵測電路與複製驅動電路是用來使介面電路能在每個資料週期內都汲取固定的動態電流而無關乎輸入資料。切換式電壓調變電路是將複製驅動電路所消耗的動態功率儲存起來並轉換成驅動電路的供應電源以減少功率消耗。而所使用的循序驅動的方式對於時脈的要求較為重要，這裡透過TSMC90RF製程實現一個用於八個傳輸通道，其操作速度為1.5GHz，相位間差距為5/8個週期，消耗功率為8.6mW，晶片面積為160×75 um2的八相位數位延遲鎖定迴路。

本論文實現的雜訊抑制介面電路相較於傳統架構下，模擬結果顯示平均來說同步切換雜訊降低為傳統的10%，時脈抖動降低為10%，因此操作速度則由原本的1Gbps提升到了6Gbps，而消耗功率增加了1.75倍。

Abstract

For high speed single-ended parallel link system, its data rate is limited to simultaneous switching noise (SSN) and cross couple noise (CCN) caused by interface circuits. To reduce SSN and CCN, this research proposes an orderly-drive parallel interface circuit. The parallel interface circuits transmit data at different phases of data period instead of simultaneously transmit data at the same phase. The current spike at power supply is averaged to all the data period thereby highly reduce SSN.

The proposed orderly-drive circuit architecture includes a delay-locked-loop (DLL), a data transition detector (TD), a replica driver (RD) and a switching type power regulator (PR). DLL generates a multi-phases clock outputs to have the parallel interface circuits transmitted data with a constant phase difference. TD and RD are used to have interface circuit periodically produces a data-independent dynamic current from power supply. PR transfer the dynamic current consumption caused by TD and RD to an internal high supply voltage used for bandwidth extension thereby improving transmission power efficiency.

To verify the proposed SSN suppression scheme, this research uses TSMC 90nm CMOS technology to design a 1.5GHz, 8-phases, all-digital DLL. The phase difference is 5/8 cycle time(225°). DLL occupies a total active area of 160μm×75μm. The test chip consumes a total power of 8.6mW.