指導老師 Advisor

A. 期刊論文 Journal 

1. Hungwen Lu, Hsinwen Wang, Chauchin Su, and Chien-Nan Jimmy Liu, “Design of an All-Digital LVDS Driver,” IEEE Transactions on CAS I, vol.56, issue.8, pp.1635-1644, August 2009.

2. Hungwen Lu, Chauchin Su, and Chien-Nan Jimmy Liu, “A Tree-Topology Multiplexer for Multiphase Clocks System,” IEEE Transactions on CAS I, vol.56, issue.1, pp.124-131, January 2009.

3. Hungwen Lu, Chauchin Su, and Chien-Nan Jimmy Liu, “A Scalable Digitalized Buffer for Gigabit I/O,” IEEE Transactions on CAS II, vol.55, issue.10, pp.1026-1030, October 2008.

B. 國際會議論文 International Conference 

• 1. Zhi-Sheng Zhang, Zhi-Yi Chen, Hung-Wen Lin,"A Buffer Circuit for the Interface of RF and Baseband System," in proceedings of IEEE International Conference on Consumer Electronics, Sep. 2021.

1. Jia-ken Li, H.-W. Lin,"A Baseband All-Digital Clock and Data Recovery Circuit with A Limited Range Binary Search FSM," in proceedings of IEEE International Conference on Consumer Electronics, Sep. 2020.

2. S.-F. Zhou, H.-W. Lin,"A 0.3V, 625Mbps Digitalized LVDS Driver in 0.18um CMOS Technology," in proceedings of IIEEE International Conference on Semiconductor Electronics, Jun. 2020.

3. Hung-Wen Lin, Jin-Yi Lin,"A Passband Lock Loop Circuit System for Band Pass Filter," in Proceedings of IEEE System on Chip Design Conference, Nov. 2016.

4. Hung-Wen Lin and Chien-Han Chuang,"A Low-Area Digitalized Low-Pass-Filter with Programmable Active-RC Load", in Proceedings of IEEE System on Chip Design Conference, Nov. 2015.

5. Ming-Chun Hsu and Hung-Wen Lin,"Heat Dissipation Improvement Design For QSFP Connector", in Proceedings of IEEE International Microsystems, Packaging, Assembly and Circuits Technology conference , Oct. 2015.

6. Hung-Wen Lin, Guan-Ru Wu, Zhi-Xiang Shao, Yong-Hsin Huang,"An 10-Gb/s Pulse-Mode I/O for On-Chip 5-mm interconnect," in Proceedings of IEEE System on Chip Design Conference, Nov. 2014.

7. Hung-Wen Lin, Wu-Wei Lin, Chun-Yen Lin,"A Low-IF AGC Amplifier for DSRC Receiver," in Proceedings of IEEE System on Chip Design Conference, Nov. 2014.

8. Hung-Wen Lin, Jin-Yi Lin, Ming-Tai Chuang,“A Low Area Digitalized Channel Selection Filter for DSRC System“ in Proceedings of IEEE International Symposia on VLSI Design, Automation and Test, April 2014.

9. Hung-Wen Lin, Hsin-Lin Hu, Wu-Wei Lin,"A DLL-Based FSK Demodulator for 5.8GHz DSRC/ETC RF Receiver"  in Proceedings of IEEE System on Chip Design Conference, Nov 2012. 

10. Hung-Wen Lu, Ying-Chieh Ho, YingLin Fa, Chau-Chin Su, “5Gb/s Pulse Signaling Interface for Low Power On-Chip Data Communication,” in Proceedings of IEEE Circuits and Systems Conference, May 2010.

11. Wei-Chang Liu, Chih-Hsien Lin, Shyh-Jye Jou, Hung-Wen Lu, Chau-Chin Su, Kai-Wei Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, Ming-Hwa Sheu, “An illustration of micro-network on chip with 10-Gb/s transmission links,” in Proceedings of Asia Solid State Circuit Conference, November 2009. 

12. Shuo-Ting Kao, Hung-Wen Lu, Chau-Chin Su, “A 1.5V 7.5uW Programmable Gain Amplifier for Multiple Biomedical Signal Acquisition,” in Proceedings of IEEE Biomedical Circuits and Systems Conference, pp.73-76, November 2009.

13. Hungwen Lu, Chauchin Su, and Chien-Nan Liu, ”A Scalable Digitalized Buffer for Gigabit I/O,” in Proceedings of Custom Integrated Circuits Conference, pp.241-244, September 2008.

14. Chauchin Su, Pocheng Lin, and Hungwen Lu, ”An Inverter Based 2-MHz 42-μW ∑∆ADC with 20-KHz Bandwidth and 66dB Dynamic Range,” in Proceedings of Asia Solid State Circuit Conference, pp.63-66, November 2006.

15. Hungwen Lu and Chauchin Su, ”A 1.25 to 5Gbps LVDS Transmitter with a Novel Multi-Phase Tree-Type Multiplexer,” in Proceedings of Asia Solid State Circuit Conference, pp. 389-392, November 2005. 

16. Hsin-Wen Wang, Hung-Wen Lu, and Chau-Chin Su, “A Self-Calibrate All-Digital 3Gbps SATA Driver Design,” in Proceedings of Asia Solid State Circuit Conference, pp. 57-60, November 2005. 

17. Wei-Da Chen, Jen-Chien Hsu, Hung-Wen Lu, and Chau-Chin Su, “A Spread Spectrum Clock Generator for SATA-II,” in Proceedings of International Symposium on Circuits and Systems, pp.2643-2646, May 2005. 

18. Hung-Wen Lu, Yin-Tin Chaung, and Chau-Chin Su, “All Digital 625Mbps & 2.5Gbps Deskew Buffer Design,” in Proceedings of International Symposium on VLSI Design, Automation and Test, pp. 258-261, April 2005. 

19. Hsin-Wen Wang, Hung-Wen Lu, and Chau-Chin Su, ”A Digitized LVDS Driver with Simultaneous Switching Noise Rejection,” in Proceedings of IEEE Asia-Pacific conference on Advanced System Integrated Circuits, pp.232-235, August 2004. 

20. Hung-Wen Lu and Chau-Chin Su, “A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type Multiplexer,” in Proceedings of IEEE Asia-Pacific conference on Advanced System Integrated Circuits, pp.228-231, August 2004.

C. 國內會議論文 Domestic Conference 

• 1. T.-H. Lin, H.-W. Lin,"A Low Voltage, Low Process Sensitivity LVDS RX Front-End," 第三十二屆超大型積體電路研討會,2021年8月

  2. Z.-S. Zhang, T.-H. Lin, H.-W. Lin,"A Low-Area Programmable Low-Pass-Filter with Automatic -3dB Frequency Calibration," 第三十屆超大型積體電路研討會,2019年8月

  3. Z.-S. Zhang, T.-H. Lin, H.-W. Lin,"A Buffer Circuit for the Interface of RF and Baseband System," 第三十屆超大型積體電路研討會,2019年8月

  4. Z.-S. Zhang, J.-H. Yan, H.-W. Lin ,"A Tunable Low-Pass Filter with Wide Bandwidth-Range Using Mixed-Mode Controls," 第二十九屆超大型積體電路研討會,2018年8月

1. J.-k. Li, Y.-L. Chen, H.-W. Lin,"A Baseband CDR circuit for Dedicated-Short-Range-Communications Systems," 第二十九屆超大型積體電路研討會,2018年8月

2. S.-F. Chou, H.-W. Lin,"A 0.35V, 500Mbps Digitalized LVDS driver in 0.18um CMOS technology," 第二十七屆超大型積體電路研討會,2016年8月

3. C.-H. Chuang, J.-K. Li, H.-W. Lin,"A Low-Area Digitalized Low-Pass-Filter with Programmable Active-RC Load," 第二十六屆超大型積體電路研討會, 2015年8月

4. J.-Y. Lin, Y.-H. Huang, H.-W. Lin,"A Passband Calibration Circuit System for Channel Selection Filter," 第二十六屆超大型積體電路研討會, 2015年8月

5. J.-S. Shao, S.-F. Zhou, H.-W. Lin, "A 1.2V 3.5Gbps Digitalized LVDS driver in 0.18um CMOS technology," 第二十六屆超大型積體電路研討會, 2015年8月(最佳論文候選)

6. H.-W. Lin, G.-R. Wu, C.-Y. Lin,"An On-Chip Impulse Mode Interface Circuit Design," 第二十五屆超大型積體電路研討會, 2014年8月

7. W.-W. Lin, H.-W. Lin, J.-K. Li,"A Band-Pass IF AGC Amplifier For DSRC System," 第二十五屆超大型積體電路研討會, 2014年8月

8. H.-W. Lin, W.-W. Lin, C.-Y. Lin, "A IF AGC Amplifier For DSRC System," 第二十五屆超大型積體電路研討會, 2014年8月

9. H.W. Lin, J.Y. Lin, M.T. Chuang, "A 40MHz IF Band Pass Filter for DSRC System,"第二十四屆超大型積體電路研討會, 2013年8月

10. H.W. Lin, M.T Chuang, "A 10bits Fast Start Up Digital Control Oscillator,"第二十四屆超大型積體電路研討會, 2013年8月

11. H.W. Lin, H.L Wu, W.W Lin, "A DLL-based FSK Demodulator for DSRC System with an Oscillator-based Delay Line,"第二十三屆超大型積體電路研討會, 2012年8月

12. H.W. Lu, C.C. Yang, J.M. Shih and C.C. Su, " A 10Gb/s/pin Transceiver for On-Chip Bus with All-Digital SerDes Scheme," 第二十一屆超大型積體電路研討會, 2010年8月. (最佳論文候選) 

13. H.W. Lu, J.M. Shih and C.C. Su, " All-Digital Resonant DCO with Inverter-based Tunable Active Inductor," 第二十一屆超大型積體電路研討會, 2010年8月. 

14. S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A Low Power Analog Front-End for Biomedical Signal Recording," 第二十屆超大型積體電路研討會, 2009年8月. (最佳論文候選) 

15. S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A 1.5-V Programmable Front-End Bio-Potential Signal Acquisition IC," 第二十屆超大型積體電路研討會, 2009年8月. 

16. H.W. Lu and C.C. Su, "A Scalable Digitalized Buffer for Gigabit I/O," 第十九屆超大型積體電路研討會, 2008年8月. 

17. H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Low Power Tree-Type Multiplexer with embedded timing skew switch, ” 第十八屆超大型積體電路研討會, 2007年8月. 

18. H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Digitalize LVDS Driver with Output Level Self-Calibrate and Pre-Emphasis,” 第十七屆超大型積體電路研討會, 2006年8月.

19. H.W. Lu and C.C. Su, "A 1.25-5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type Multiplexer," 第十六屆超大型積體電路研討會, 2005年8月.

20. H.W. Lu and C.C. Su, “A 2.5Gbps Digitalize LVDS Transceiver design,” 第十五屆超大型積體電路研討會, 2004年8月. 

21. H.W. Wang, H.W. Lu and C.C. Su, “A Digitized LVDS Driver with Simultaneous Switching Noise Rejection, ” 第十五屆超大型積體電路研討會, 2004年8月. 

22. H.W. Lune and C.C. Su, "A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type Multiplexer," 第十四屆超大型積體電路研討會, 2003年8月.

D. 專利 Patent 

• • 美國專利 USA

1. No.10063236, Dec. 13, 2016, Hung-Wen Lin Shih-Fang Jhou and Chih-Hsiang Shao,"Low-voltage differential signaling transmitter and receiver. " 

2. No.7843276, Nov. 30, 2010. Hung-Wen Lu and Chau-Chin Su, “Oscillator circuit.”

3. No.7977993, July 12, 2011. Hung-Wen Lu and Chau-Chin Su, “Signal delay circuit.”

4. No.7912166, Mar. 22, 2011. Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang, “Built-in jitter measurement circuit.”

5. No.7495479, Feb. 24, 2009. Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang, “Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit.”

6. No.7,474,239, January 6, 2009. Chau-Chin Su, Hung-Wen Lu, Shun-Min Chi, “Self-Calibrating High-Speed Analog-to-Digital Converter.”

7. No.7,764,086, July 27, 2010, Hung-Wen Lu and Chau-Chin Su, “Buffer circuit.”

8. No.7,415,089, August 19, 2008. Chau-Chin Su, Cheinhsi Lee, Hung-Wen Lu, Hsueh-Chin Lin, Yen-Pin Tseng, Chia-Nan Wang, Uan-Jiun Liu, ”High-speed serial link clock and data recovery”

   • 台灣專利 TAIWAN

9. 專利號碼:I599173, 2017年9月, 林鴻文,周世芳,邵致翔,"低電壓差動訊號模式發射與接收電路"

10. 專利號碼:286016, 2007年8月, 蘇朝琴,李建錫,呂鴻文, ”傳輸機之時脈與資料回復裝置與其操作方法”

11. 專利號碼:272770, 2007年2月. 蘇朝琴,陳俊銘,呂鴻文, ”多相位數位控制震盪器.”

12. 專利號碼:268055, 2006年12月. 蘇朝琴,李建錫,呂鴻文,林學錦,曾硯彬,王家男,劉萬鈞, ”高速串列鏈結時脈及資料回復系統及方法”

13. 專利號碼:241766, 2005年10月1日. 蘇朝琴, 王信文, 呂鴻文, ”可抑制同步切換雜訊電路.”

14. 專利號碼:239144, 2005年9月1日. 蘇朝琴,呂鴻文,莊英廷,”通訊傳輸機之數位相為校正緩衝器與其操作方法.”

    • 中國大陸專利 CHINA

15. 公 开号: CN101207379, 2007.12.21, 吕鸿文;苏朝琴, “缓冲器电路”

16. 公 开号: CN101359014, 2007.7.31, 吕鸿文;苏朝琴, “内建抖动测量电路”

17. 公 开号: CN101499790, 2008.1.28, 吕鸿文;苏朝琴, “信号延迟电路 ”

18. 公 开号: CN101499800, 2008.1.28, 吕鸿文;苏朝琴, “振荡电路 ”

E. 學術服務 Academic activity

    論文審查 (Paper Review)

1. 2018/05 ~ 2018/06, IEEE Transaction On Circuit and System II, Reviewer

   1. 2018/05 ~ 2018/06, Microelectronics Journal, Reviewer

   2. 2018/02 ~ 2018/02, 2018 Symposia on VLSI Technology and Circuits, Reviewer

   3. 2017/12 ~ 2018/01, Microelectronics Journal, Reviewer

   4. 2017/09 ~ 2017/09, Microelectronics Journal, Reviewer

   5. 2017/02 ~ 2017/02, 2017 Symposia on VLSI Technology and Circuits, Reviewer

2. 2016/06 ~ 2016/07, 2016 IEEE Asia Pacific Conference on Circuits and Systems, Reviewer

3. 2016/02 ~ 2016/02, 2015 Symposia on VLSI Circuits, Reviewer

4. 2015/07 ~ 2015/08, IEEE Transaction On Circuit and System I, Reviewer

5. 2015/07 ~ 2015/08, IEEE Transaction On VLSI Systems, Reviewer

6. 2015/02 ~ 2015/02, 2015 Symposia on VLSI Circuits, Reviewer

7. 2014/02 ~ 2014/04, IEEE Transaction On Circuit and System I, Reviewer

8. 2014/01 ~ 2014/01, 2014 Symposia on VLSI Circuits, Reviewer

9. 2013/12 ~ 2014/01, 2014 International Symposium on Circuits and Systems, Reviewer

10. 2013/01 ~ 2013/01, 2013 Symposium on VLSI Circuits, Reviewer

11. 2012/11 ~ 2013/02, IEEE Transaction On Circuit and System I, Reviewer

12. 2010/07 ~ 2010/12, Circuits, Systems & Signal Processing, Reviewer

13. 2010/07 ~ 2010/12, Microelectronics Journal, Reviewer

14. 2010/07 ~ 2010/12, IEEE Transactions on Circuits and Systems I, Reviewer

    研討會主持 (Session Chair)

1. 2020/08 ~ 2020/08, 2019 TICD 31th VLSI Design/CAD Symposium, Session Oral S2: "Power, Sensor, and Other Analog Techniques", Session Chair

2. 2019/08 ~ 2019/08, 2018 TICD 30th VLSI Design/CAD Symposium, Session Oral S2: "Power, Sensor, and Other Analog Techniques", Session Chair

3. 2018/08 ~ 2018/08, 2018 TICD 29th VLSI Design/CAD Symposium, Session Oral S6: "Circuits and Systems for Communication Ics", Session Chair

4. 2018/08 ~ 2018/08, 2018 TICD 29th VLSI Design/CAD Symposium, Technique Program Committee.

5. 2017/08 ~ 2017/08, 2017 TICD 28th VLSI Design/CAD Symposium, Session S9: "PLLs, DLLs and Wireless Transceivers", Session Chair

6. 2017/08 ~ 2017/08, 2017 TICD 28th VLSI Design/CAD Symposium, Technique Program Committee.

7. 2016/11 ~ 2016/11, 2016 IEEE International SoC Design Conference, "Wireless and RF ICs", Session Chair

8. 2016/08 ~ 2016/08, 2016 TICD 27th VLSI Design/CAD Symposium, Session 5: "Advanced Testing and Diagnosis", Session Chair

9. 2016/08 ~ 2016/08, 2016 TICD 27th VLSI Design/CAD Symposium, Technique Program Committee.

10. 2015/08 ~ 2015/08, 2015 TICD 26th VLSI Design/CAD Symposium, Session 12: "I/O and Biomedical Circuits", Session Chair

11. 2015/04 ~ 2015/08, 2014 TICD 26th VLSI Design/CAD Symposium, Technique Program Committee

12. 2014/11 ~ 2014/11, 2014 IEEE International System On Chip design Conference, Regular session  "Analog and Mixed-Signal Techniques I", Session chair

13. 2014/08 ~ 2014/08, 2014 TICD 25th VLSI Design/CAD Symposium, Session 10: "Wired and Wireless Technique", Session Chair

14. 2014/04 ~ 2014/08, 2014 TICD 25th VLSI Design/CAD Symposium, Technique Program Committee

15. 2012/11 ~ 2012/11, 2012 IEEE International System On Chip design Conference, Regular session 6 "analog and mixed signal circuit", Session chair

E. 非學術服務 

1. 2018/08 ~ 2019/07, 中華民國國家標準(CNS)電子工程委員會委員

2. 2018/02 ~ 2018/02, 經濟部標準檢驗局107年度「團體推動標準化活動補助專案」計畫審查人

3. 2017/02 ~ 2017/02, 經濟部標準檢驗局 106年度「團體推動標準化活動補助專案」計畫審查人

4. 2015/07 ~ 2017/06, 中華民國國家標準(CNS)電子工程委員會委員

5. 2013/07 ~ 2015/07, 中華民國國家標準(CNS)電子工程委員會委員

6. 2017/12 ~ 2018/05, 106學年度全國大學院校積體電路設計競賽, 審查委員

7. 2016/12 ~ 2017/05, 105學年度全國大學院校積體電路設計競賽, 審查委員

8. 2016/01 ~ 2015/05, 104學年度全國大學院校積體電路設計競賽, 審查委員

9. 2015/01 ~ 2015/06, 103學年度全國大學院校積體電路設計競賽, 審查委員

10. 2014/01 ~ 2014/06, 102學年度全國大學院校積體電路設計競賽, 審查委員

F. 榮譽 Award

1. 2015/11/2  Silicon Mitus paper award, 2015 IEEE International System-On-Chip Design Conference.

2. 2015/8/2  第二十六屆超大型積體電路研討會,最佳論文候選, 紹致翔, 周世芳, 林鴻文.

3. 2014/7/10  102學年度全國大學院校積體電路設計競賽 研究所全客戶設計組，佳作，林金誼、胡心麟

4. 2014/7/10  102學年度全國大學院校積體電路設計競賽 研究所全客戶設計組，佳作，黃永興、莊承翰

5. 2013/8/6  晶片設計中心2012年度優等設計獎，設計名稱: 應用於特定短距通訊系統之中頻帶通濾波器，林金誼、莊明泰

6. 2013/8/6  晶片設計中心2012年度優等設計獎，設計名稱: 一個快速起振的十位元數位控制震盪電路，莊明泰

7. 2012/11/5  SK Hynix paper award, 2012 IEEE International System-On-Chip Design Conference

8. 工業技術研究院98年度優質專利，” Method and Apparatus for Clock / Data Recovery by using Oversampling techniques”, 蘇朝琴、李建錫、呂鴻文。

9. 2009/11/18  亞洲固態電子電路會議2009年學生設計競賽優勝,” An illustration of micro-network on chip with 10-Gb/s transmission links”, 劉偉昌、林志憲、周世傑、呂鴻文、蘇朝琴、洪凱蔚、鄭國興、許明華。

10. 2009/5/3  晶片設計中心2008年度佳作設計獎，設計名稱: 一個無被動電感與被動電容的數位控制店感電容式震盪電路 A LC tank Digital Control Oscillator without Passive Inductor ，呂鴻文、史汝敏、蘇朝琴、劉建男。

11. 工業技術研究院97年度優質專利，”Buffer circuit”，呂鴻文、蘇朝琴。

12. 2007/5/3  晶片設計中心2006年度優良設計獎，設計名稱: 低功率低面積的全新樹狀序列器 A 10Gbps Tree-Type Multiplexer Design”，陳冠宇、呂鴻文、蘇朝琴、劉建男。

13. 2004/4/21 晶片設計中心2003年度優良設計獎，設計名稱: 625MHz低功率小面積全數位相位校正緩衝器 ”All Digital 625Mbps & 2.5Gbps Deskew Buffer Design，莊英廷、呂鴻文、蘇朝琴、劉建男。

    1. 2004/4/21  晶片設計中心2003年度佳作設計獎，設計名稱: 可自我校正全數位 A Self-Calibrate All-Digital 3Gbps SATA Driver Design，王信文、呂鴻文、蘇朝琴、劉建男。

14. 2003/4/23  晶片設計中心2002年度優良設計獎，設計名稱: 5Gbps低壓差動訊號傳輸器 A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type Multiplexer” ，呂鴻文、徐仁乾、蘇朝琴、劉建男。

G. 歷年開授課程 Teaching experience

• 1. 2016/9~2017/2  1051  電路學1, 數位超大型積體電路

  2. 2016/2~2016/7  1042  電子電路實驗 2 , 寬頻介面積體電路

1. 2015/9~2016/2  1041  電子學1, 數位超大型積體電路 

2. 2015/2~2015/7  1032  電子電路實驗 2 , 寬頻介面積體電路

3. 2014/9~2015/1  1031  電子電路實驗 1 , 數位超大型積體電路 , 書報討論

4. 2014/2~2014/7  1022  電子電路實驗 2 , 微感測器及感測電路設計 

5. 2013/9~2014/1  1021  電子電路實驗 1 , 電路學 1 , 數位超大型積體電路設計

6. 2013/2~2013/7  1012  電子電路實驗 2 , 電路學 2 , 寬頻介面積體電路 

7. 2012/9~2013/1  1011  電子電路實驗 1 , 電路學 1 , 數位超大型積體電路設計 , 工程數學 1 , 電機專題

8. 2012/2~2012/7  1002  普通物理實驗 2 , 電路學 2 , 程式語言 , 訊號與系統 

9. 2011/9~2012/1  1001  普通物理實驗 1 , 電路學 1 , 寬頻介面積體電路 , 電機專題 

10. 2011/2~2011/7    992  普通物理實驗 2 , 電路學 2 , 程式語言 

11. 2010/9~2011/1    991  普通物理實驗 1 , 電路學 1 , 寬頻介面積體電路 

12. 2009/2~2010/7    982  普通物理實驗 2 , 書報討論 , 程式語言