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本實驗室成立於2010年，位於元智大學7館635室，指導老師是林鴻文博士。專注於高性能類比(Analog)與混合信號(Mixed-Signal)積體電路設計與實現，應用於商用高速或低功率通訊系統

目前研究主題包含如下(可點擊進入):

1. 低功率/高速 晶片內/晶片間 傳輸介面電路模組設計

2. 特定短距通訊(DSRC)系統之中頻調變(Modulator)/解調變器(Demodulator)/帶通濾波器(Filter)電路設計

3. 高速序列介面電路模組的自我校正(self calibration)、自我功率最佳化

4. 可程式化/全數位 時脈產生電路設計

訓練學生在 "電路模擬"、"架構設計與特性分析"、"電路佈局"、"晶片量測"等 面向的專業技能，並期許學生能成為產業界及學術界所需之積體電路設計人才

High-Speed-Integrated-Circuit laboratory (HSIC Lab.) was set up by Dr. Hung-Wen Lin since july 2010. This Lab. is now located at room No.635 of Building No.7 in YuanZe university.

The research field of HSIC lab is high performance mixed-signal mode integrated circuit. 

More specifically, focus on the design of high-speed and low-power interface circuit.

Here are several research topics under going:

1.High power-efficiency interface for on-chip bus

  -Pulse-mode interface circuit

  -Adaptive equalizer and pre-emphasis

2.Parallel Input/Output (I/O) buffer design

  -Low simultaneous switching noise (SSN) circuit

  -Cross-talk compensation

3. Dedicated Short Range Communication (DSRC) system Intermediate-Frequency (IF) module design

  -Frequency Shift Keying modulator / Demodulator

  -Pulse shaping filter / Gaussian filter / Channel select filter

  -Auto-gain-control (AGC) amplifier / Receiver signal strength indicator (RSSI)

  -Analog-to-digital converter (ADC) / Digital-to-analog converter (DAC)

4.Self calibration circuit and built-in-self-test circuit (BIST) for interface circuit.

5.Clock multiplier / frequency synthesizer

  -Programmable & digitalized architecture

  -Delay-lock-loop (DLL)/ phase-lock-loop (PLL)

HSIC Lab. provides basic but complete training of integrated circuit design. 

All the members are asked to independently finish the test chip according to the IC design flow as shown in the following figures.

測試電路版設計與實作 

Test PCB Design & Implementation

系統模擬 Behavior-Level Design & Simulation

電路架構設計 Transistor-Level Circuit Design

電路時域與頻域特性分析

Time-Domain Simulation

Transistor-Level Simulation

晶片量測 Chip Measurement

Frequency-Domain Simulation

電路佈局 Transistor-Level Circuit Layout

測試晶片實現 Chip Implementation