JOURNAL PUBLICATIONS

1. J. S. Yuan, J. J. Liou, and W. R. Eisenstadt, “A physics-based current-dependent base resistance model for advanced bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-35, pp. 1055-1062, July 1988

2. J. J. Liou and J. S. Yuan, “A two-dimensional model for emitter-base junction capacitance of bipolar transistors,” Solid-State Electron., vol. 31, pp. 1541-1549, October 1988

3. J. S. Yuan and W. R. Eisenstadt, “S-parameter measurement prediction for bipolar transistors using a physical device simulator,” IEEE Trans. Electron Devices, vol. 35, pp. 1633-1639, October 1988

4. J. S. Yuan and W. R. Eisenstadt, “Circuit modeling of collector current spreading effects in quasi-saturation for advanced bipolar transistors,” Solid-State Electron., vol. 31, pp. 1725-1731, December 1988

5. J. J. Liou, A. Whittaker, and J. S. Yuan, “Modeling the two-dimensional emitter-base and base-collector junction capacitances of bipolar junction transistors,” Phys. Stat. Sol., vol. 113, pp. 267-271, June 1989

6. J. S. Yuan and J. J. Liou, “Circuit modeling of transient emitter crowding and dynamic resistance effects for advanced bipolar transistors,” Solid-State Electron., vol. 32, pp. 623-631, August 1989

7. J. J. Liou and J. S. Yuan, “A physics-based bipolar transistor model for low-temperature circuit simulation,” J. Appl. Phys., vol. 66(9), pp. 4474-4480, November 1989

8. J. J. Liou and J. S. Yuan, “An avalanche multiplication model for bipolar transistors,” Solid-St. Electron., vol. 33, pp. 35-37, January 1990

9. J. J. Liou and J. S. Yuan, “Compact bipolar transistor model for circuit simulation,” Int. J. Electron., vol. 68, pp. 265-273, February 1990

10. J. S. Yuan, W. R. Eisenstadt, and J. J. Liou, “A novel lossy and dispersive interconnect model for integrated circuit simulation,” IEEE Trans. Components, Hybrids, and Manufac. Tech., vol. 13, pp. 275-280, June 1990

11. J. J. Liou, W. W. Wang, and J. S. Yuan, “A study of base built-in field effects on the steady-state current gain of heterojunction bipolar transistors,” Solid-St. Electron., vol. 33, pp. 845-849, July 1990

12. J. S. Yuan and J. J. Liou, “An improved latching pulse design for dynamic sense amplifiers,” IEEE J. Solid-State Circuits, vol. SC-25, pp. 1294-1299, October 1990

13. J. J. Liou and J. S. Yuan, “Modeling the reverse base current phenomenon due to avalanche effect in advanced bipolar transistors,” IEEE Trans. Electron Devices, vol. 37, pp. 2274-2276, October 1990

14. J. J. Liou, J. S. Yuan, and W. W. Wong, “Effects of using the more accurate intrinsic concentration on bipolar transistor modeling,” J. Appl. Phys., vol. 68(11), pp. 1911-1912, December 1990

15. J. J. Liou, K. Lee, S. M. Knapp, K. B. Sundaram, J. S. Yuan, D. C. Malocha, M. Belkerdid, “A non-quasi-static small-signal model for metal-semiconductor junction diode,” Solid-State Electron., vol. 33, pp. 1629-1632, December 1990

16. J. S. Yuan and J. J. Liou, “An improved Early voltage model for advanced bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-38, pp. 179-182, January 1991

17. J. J. Liou and J. S. Yuan, Physics-based large-signal heterojunction bipolar transistor model for circuit simulation,” IEE Proceedings, Part G, vol. 138, pp. 97-103, February 1991

18. J. S. Yuan, W. R. Eisenstadt, and J. J. Liou, “Modeling of coupled interconnect Lines for integrated circuits,” Int. J. Electron., vol. 70, pp. 751-764, April 1991

19. J. S. Yuan and J. J. Liou, “Modeling of temperature-dependent avalanche currents in advanced bipolar transistors,” Solid-State Electron., vol. 34, pp. 533-534, May 1991

20. J. S. Yuan, “Two-dimensional lateral bipolar transistor model for circuit simulation,” Int. J. Electron., vol. 70, pp. 1041-1048, June 1991

21. J. S. Yuan, C. S. Yeh, and B. Gadepally, “Temperature and impact ionization effects on fT of advanced bipolar transistors,” J. Appl. Phys., vol. 70(4), pp. 2402-2407, August 1991

22. J. S. Yuan, “Modeling the current-dependent fT for AlGaAs/GaAs heterojunction bipolar transistor design,” Solid-State Electron., vol. 34, pp. 1103-1107, October 1991

23. J. S. Yuan, “Optimal CMOS interconnect width design in electromigration free,” Int. J. Electron., vol. 71, pp. 771-779, November 1991

24. J. S. Yuan, “High performance P-n-p heterojunction bipolar transistor design,” Solid-St. Electron., vol. 34, pp. 1347-1352, December 1991

25. J. S. Yuan, C. S. Yeh, and B. Gadepally, “Effects of using minority hole mobility in n+ emitter on bipolar transistor modeling,” Solid-State Electron., vol. 34, pp. 1460-1462, December 1991

26. J. S. Yuan, “Delay analysis of BiNMOS driver including high current transients,” IEEE Trans. Electron Devices, vol. ED-39, pp. 587-592, March 1992

27. J. J. Liou, J. S. Yuan, and S. Hooman, “Modeling of the bipolar transistors subjected to neutron irradiation for circuit simulation,” IEEE Trans. Electron Devices, vol. 39, pp. 593-597, March 1992

28. J. S. Yuan and J. J. Liou, “Improved bipolar model equations for small-signal circuit simulation,” Int. J. Electron., vol. 72, pp. 619-630, May 1992

29. J. J. Liou and J. S. Yuan, “Surface recombination current of AlGaAs/GaAs Heterojunction bipolar transistors,” Solid-State Electron., vol. 35, pp. 805-813, June 1992

30. J. J. Liou and J. S. Yuan, “Optically driven photoconductive devices for power switching application, Part II: thermal modeling including heat sink,” IEE Proceedings, Part G, vol. 139, pp. 350-355, June 1992

31. J. S. Yuan, “Modeling of Si/Si1-xGex heterojunction bipolar transistors,” Solid-State Electron., vol. 35, pp. 921-926, July 1992

32. J. S. Yuan, “Collector-base junction capacitance of advanced bipolar transistors operating at avalanche breakdown,” Physica Status Solidi, vol. 134, pp. 575-581, December 1992

33. J. S. Yuan, “Modeling of GaAs MESFET output conductance and transconductance frequency dispersion,” Int. J. Electron., vol. 74, pp. 51-58, January 1993

34. J. S. Yuan, “Testing the impact of process defects on ECL power-delay performance,” Int. J. Electron., vol. 74, pp. 201-207, February 1993

35. J. S. Yuan and J. J. Liou, “Array noise analysis for megabit DRAM's,” Int. J. Electron., vol. 74, pp. 265-279, February 1993

36. J. S. Yuan, “Base pushout effect on collector signal delay and Early voltage for heterojunction bipolar transistors,” Solid-State Electron., vol. 36, pp. 657-660, April 1993

37. J. S. Yuan, “Avalanche breakdown effects on AlGaAs/GaAs HBT performance,” Int. J. Electron., vol. 74, pp. 909-916, June 1993

38. J. S. Yuan, “Comment on "AlGaAs/GaAs HBT for high-temperature applications,”” IEEE Trans. Electron Devices, vol. ED-40. p. 1717, September 1993

39. J. S. Yuan, “Switch-off transient analysis for heterojunction bipolar transistors in saturation,” Solid-State Electron., vol. 36, pp. 1261-1266, September 1993

40. J. A. Blanchard and J. S. Yuan, “Effect of collector current exponential decay on power efficiency for class E tuned power amplifier,” IEEE Trans. Circuits and Systems, vol. CAS-41, pp. 69-71, January 1994

41. J. S. Yuan, “Effect of base profile on the base transit time of the bipolar transistor for all levels of injection,” IEEE Trans. Electron Devices, vol. ED-41, pp. 212-216, February 1994

42. J. S. Yuan, “Low temperature BiCMOS gate pull down delay analysis,” Int. J. Electron., vol. 76, pp. 221-232, February 1994

43. J. S. Yuan, “Base current reversal in bipolar transistors and circuits: a review and update,” IEE Proceedings, Part G, vol. 141, pp. 299-306, August 1994

44. J. S. Yuan, “Modeling the bipolar oscillator phase noise,” Solid-State Electron., vol. 37, pp. 1765-1768, October 1994

45. J. S. Yuan and J. Ning, “Effect of impact ionization on CJC of heterojunction bipolar transistors,” Solid-State Electron., vol. 3, pp. 742-744, March 1995

46. J. S. Yuan, “An integral Gummel relation for single and double-heterojunction graded-base HBT's,” Physica Status Solidi, vol. 147, pp. 643-650, April 1995

47. J. S. Yuan, “Thermal and reverse base current effects on heterojunction bipolar transistors and circuits,” IEEE Trans. Electron Devices, vol. 43, pp. 789-794, May 1995

48. J. S. Yuan, Y. Dai, Y. Gu, and J. Ning, “The bipolar junction transistor in saturation,” Physica Status Solidi, vol. 149, pp. 757-769, June 1995

49. J. S. Yuan and J. Ning, “Analysis of abrupt and linearly-graded heterojunction bipolar transistors with or without a setback layer,” IEE Proceedings, Part G, vol. 142, pp. 254-262, August 1995

50. J. S. Yuan and Y. Gu, “Transient analysis of bipolar transistors including built-in field and recombination in quasi-neutral base,” Physica Status Solidi, vol. 153, pp. 287-297, January 1996.

51. J. S. Yuan, “Study of AlGaAs/InGaAs pseudomorphic HEMT using a two-dimensional device simulator,” Physica Status Solidi, vol. 153, pp. 559-566, January 1996

52. A. M. Phanse, J. S. Yuan, C.-S Yeh, and B. Gadepally, “Modeling of BiCMOS switching delay including effects of radiation,” IEE Proceedings, vol. 144, pp. 53-59, April 1997

53. J. Song and J. S. Yuan, “Comment on “On the base profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications - part II: circuit performance issues,”” IEEE Trans. Electron Devices, vol. ED-44, pp. 915-917, May 1997

54. H. D. Pham and J. S. Yuan, “Circuit analysis of BiCMOS gate delay,” Int. J. Electronics, pp. 1-12, July 1997

55. Y. Dai and J. S. Yuan, “Base transit time of the bipolar transistor in quasi-saturation,” IEEE Trans. Electron Devices, vol. ED-44, 1558-1560, September 1997

56. J. H. Ning, J. S. Yuan, and J. Song, “Effects of base and emitter doping gradients on the electrical performance of heterojunction bipolar transistors,” Solid-State Electronics, vol. 41, pp. 1263-1268, September 1997

57 J. Song and J. S. Yuan, “Optimum Ge profile for base transit time minimization of SiGe HBT,” Solid-State Electronics, vol. 41, pp. 1957-1959, December 1997

58. Y. Dai and J. S. Yuan, “Current-dependent collector resistance of the bipolar transistor in quasi-saturation,” IEE Proceedings, Part G, 66-70, April 1998

59. Y. Dai and J. S. Yuan, “Comparison of Gummel-Poon and quasi-saturation models in BiCMOS switching delay,” Int. J. Electronics, pp. 307-319, April 1998

60. Y. Gu and J. S. Yuan, “Gate-oxide thickness effects on hot-carrier-induced degradation in n-MOSFETs,” Int. J. Electronics, 1-9, May 1998

61. J. S. Yuan, Y. Dai, and C.-S. Yeh, “A scalable bipolar transistor model for circuit simulation,” Physica Status Solidi, (a) 268, pp. 209-222, July 1998

62. M. M. Mahin and J. S. Yuan, “Modeling of avalanche current including non-local effect,” Int. J. Electron, vol. 85, No. 4, pp. 409-417, August 1998

63. J. Song and J. Yuan, “Modeling the base-collector heterojunction barrier effect at high current densities of SiGe HBTs,” Solid-State Electron., vol. 43, pp. 457-461, January 1999

64. J. Song and J. S. Yuan, “Graded base profiles on the performance of AlxGa1-xAs/AlyGa1-yAs HBT’s”, Int. J. Electron., vol. 86, pp. 699-705, June 1999

65. R. Awadalla and J. S. Yuan, “A new structure design of a silicon-on-insulator MOSFET reducing the self-heating effect,” Int. J. Electron., vol. 86, pp. 707-712, June 1999

66. X. Duan, W. Luo, W. Wu, and J. S. Yuan, “Dielectric response of ferroelectric relaxors,” Solid-St. Communication, vol. 114, pp. 597-600, June 2000

67. X. Duan and J. S. Yuan, “Modeling gate oxide breakdown under bipolar stress,” Solid-State Electron., vol. 44, pp. 1537-1541, September 2000

68. X. Duan and J. S. Yuan, “Conduction-band deformation effect on stress-induced leakage current,” Solid-State Electron., vol. 44, pp. 1703-1706, September 2000

69. W. Li, J. S. Yuan, S. Chetlur, J. Zhou, and A. S. Oates, “An improved substrate current model for deep submicron MOSFETs,” Solid-St. Electron., vol. 44, pp. 1985-1988, November 2000

70. J. Zhang, J. S. Yuan, and Y. Ma, “Modeling short channel effect on high-k and stacked gate MOSFETs,” Solid-State Electron., vol. 44, pp. 2089-2091, November 2000

71. J. Zang, J. S. Yuan, Y. Ma, and A. Oates, “Design optimization of stacked layer dielectrics for deep submicron MOSFETs,” Solid-State Electron., vol. 44, pp. 2165-2170, December 2000

72. W. Wu, S. H. Kang, J. S. Yuan, and A. S. Oates, “Thermal effect on electromigration performance for Al/SiO2, Cu/SiO2, and Cu/low-K interconnect systems,” Solid-State Electron., vol. 45, pp. 59-62, January 2001

73 J. Zhang, J. S. Yuan, Y. Ma, and T. Oates, “Modeling of direct tunneling and surface roughness effects on C-V characteristics of ultra-thin gate MOS capacitors,” Solid-State Electron., vol. 45, pp. 373-377, February 2001

74. Q. Li, J. Zhang, W. Li, J. S. Yuan, Y. Chen, and A. Oates, “RF circuit performance degradation due to soft breakdown and hot carrier effect in deep submicron CMOS Technology,” IEEE Trans. Microwave Theory and Technologies, vol. MTT-49, pp. 1546-1551, September 2001

75. J. Zhang, J. S. Yuan, Y. Ma, Y. Chen, and A. Oates, “Experimental evaluation of device degradation subject to oxide soft breakdown,” Solid-State Electron., vol. 45, pp. 1521-1524, September 2001

76. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Delay-insensitive gate-level pipelining,” Integration, the VLSI Journal, vol. 32, pp. 103-131, November 2001

77. W. Wu and J. S. Yuan, “Copper electromigration modeling including barrier layer effect,” Solid-State Electron., vol. 45, pp. 2011-2016, December 2001

78. W. Wu, J. S. Yuan, S. H. Kang, and A. S. Oates, “Electromigration subjected to Joule heating and pulsed-dc stress,” Solid-State Electronics, vol. 45, pp. 2051-2056, December 2001

79. Q. Li, J. Zhang, W. Li, and J. S. Yuan, “Linearity analysis and design optimization for 0.18 m CMOS RF mixer,” IEE Proceedings, vol. 149, pp. 112-118, April 2002

80. W. Wu and J. S. Yuan, “Skin effect of on-chip copper interconnects on electromigration,” Solid-State Electron., vol. 46, pp. 2269-2272, December 2002

81. E. Xiao, J. S. Yuan, and H. Yang, “Effects of hot carrier stress and oxide soft breakdown on VCO performance,” IEEE Trans. Microwave Theory and Techniques, vol. MTT-50, pp. 2453-2458, November 2002

82. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation,” J. Systems Architecture, vol. 47/12, pp. 977-998, February 2003

83. Kuang, J.S. Yuan, R. DeMara, M. Hagedorn, and K. Fant, “Performance analysis and optimisation of NCL self-timed rings,” IEE Proceedings, vol. 150, pp. 167-172, June 2003

84. W. Wu, X. Duan, and J. S. Yuan, “Modeling of time-dependent dielectric breakdown in copper metallization,” IEEE Trans. Device and Materials Reliability, vol. TDMR-3, pp. 26-30, June 2003

85. H. Yang, J. S. Yuan, Y. Liu, and E. Xiao, “Effect of gate oxide breakdown on RF performance,” IEEE Trans. Device and Materials Reliability, vol. TDMR-3, pp. 93-97, September 2003

86. E. Xiao, J. S. Yuan, and H. Yang, “CMOS RF and DC reliability subject to hot carrier stress and oxide soft breakdown,” IEEE Trans. Device and Materials Reliability, vol. TDMR-4, pp. 92-98, March 2004

87. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, “Optimization of NULL convention self-timed circuits,” Integration, the VLSI Journal, vol. 37, pp. 135-165, August 2004

88. J. S. Yuan and W. Kuang, “Teaching asynchronous design in digital integrated circuits,” IEEE Trans. Education, vol. TE-47, pp. 397-404, August 2004

89. W. Kuang and J. S. Yuan, “Energy-efficient self-timed circuit design using supply voltage scaling,” IEE Proceedings, vol. 151, pp. 278-284, August 2004

90. J. Di, J. S. Yuan, and M. Hagedorn, “Analytical input mapping for modelling energy dissipation of complex CMOS gates,” IEE Proceedings, vol. 151, pp. 294-299, August 2004

91. L. Yang and J. S. Yuan, “Modelling and analysis of ground bounce due to internal gate switching,” IEE Proccedings, vol. 151, pp. 300-306, August 2004

92. C. Yu, Y. Liu, A. Sadat, and J. S. Yuan, “Impact of temperature accelerated voltage stress on PMOS RF performance,” IEEE Trans. Device and Materials Reliability, vol. 4, pp. 664-669, December 2004

93. C. Yu, J. S. Yuan, and H. Yang, “MOSFET linearity performance degradation subject to drain and gate voltage stress,” IEEE Trans. Device and Materials Reliability, vol. 4, pp. 681-689, December 24, 2004

94. J. S. Yuan and L. Yang, “Teaching digital noise and noise margin issues in electrical engineering education,” IEEE Trans. Education, vol. 48, pp. 162-168, February 2005

95. J. S. Yuan and J Di, “Teaching low power electronic design in electrical and computer engineering,” IEEE Trans. Education, vol. 48, pp. 169-182, February 2005

96. A. Sadat, Y. Liu, C Yu, and J. S. Yuan, “Analysis and modelling of LC oscillator reliability,” IEEE Trans. Device and Materials Reliability, vol. 5, pp. 119-128, March 2005

97. C. Yu, H. Yang, E. Xiao and J. S. Yuan, “Voltage stress-induced performance degradation in NMOSFET mixer”, IEICE Electron. Express, vol. 2, pp.133-137, March 2005

98. L. Yang and J. S. Yuan, “Output buffer design for low noise and load adaptability,” IEE Proceedings, vol. 152, pp. 146-150, April 2005

99. Y. Liu, A. Sadat, and J. S. Yuan, “Gate oxide breakdown on MOSFET cutoff frequency and breakdown resistance,” IEEE Trans. Device and Materials Reliability, vol. 5, pp. 282-288, June 2005

100. L. Yang and J. S. Yuan, “Decoupling technique for CMOS gate with strong coupled components,” IEE Proceedings, vol. 152, pp. 279-286, June 2005

101. C. Yu and J. S. Yuan, “MOS RF reliability subject to dynamic voltage stress - modeling and analysis,” IEEE Trans. Electron Devices, vol. 52, pp. 1751-1758, August 2005

102. E. Xiao, P. Ghosh, C. Yu, and J. S. Yuan, "Hot carrier and soft breakdown effects on LNA performance for ultra wideband communications,” Microelectronics Reliability, vol. 45, pp. 1382-1385, October 2005

103. C. Yu, E. Xiao, and J. S. Yuan “Voltage stress-induced hot carrier effect on SiGe HBT VCO,” Microelectronics Reliability, vol. 45, pp. 1402-1405, October 2005

104. C. Yu, J. S. Yuan, and A. Sadat, “Dynamic-stress-induced high-frequency noise degradations in nMOSFETs,” Microelectronics Reliability, vol. 45, pp. 1794-1799, October 2005

105. A. Sadat, H. Qu, C. Yu, J. S. Yuan, and H. Xie, “Low power CMOS wireless MEMS motion sensor for physiological activity monitoring,” IEEE Trans. Circuits and Systems, vol. 52, pp. 2539-2551, December 2005

106. J. S. Yuan and H. Yang, “Device reliability characterization for electrical engineering curriculum,” Int. J. Electrical Engineering Education, pp. 67-79, January 2006

107. J. Di, J. S. Yuan, and R. DeMara, “Improving power-awareness of pipelined array multipliers using 2-dimensional pipeline gating and its application to FIR design,” Integration, the VLSI Journal, vol. 39, pp. 90-112, March 2006

108. J. Di and J. S. Yuan, “Energy-aware design for multi-rail encoding using NCL,” IEE Proceedings, vol. 153, pp. 100-106, April 2006

109. C. Yu and J. S. Yuan, “Channel hot electron degradation on 60 nm HfO2-gated nMOSFET DC and RF performances,” IEEE Trans. Electron Devices, vol. 53, pp. 1065-1072, May 2006

110. J. Di and J. S. Yuan, “Energy-aware dual-rail bit-wise completion pipelined arithmetic circuit design,” Journal of Low Power Electronics, vol. 2, pp. 1-16, August 2006

111. C. Yu, J. S. Yuan, and E. Xiao, “Dynamic voltage stress effects on nMOS varactor,” Microelectronics Reliability, pp. 1812-1816, October 2006

112. C. Yu, L. Jiang, and J. S. Yuan, “Study of performance degradations in DC-DC converter due to hot carrier stress by simulation,” Microelectronics Reliability, pp. 1840-1843, October 2006

113. C. Yu, J. S. Yuan, J. Shen, and E. Xiao, “Study of electrical stress effect on SiGe HBT low-noise amplifier performance by simulation,” IEEE Trans. Device and Materials Reliability, pp. 550-555, December 2006

114. C. Yu, J. Zhang, J. S. Yuan, F. Duan, S. K. Jayanarananan, A. Marathe, S. Cooper, V. Pham, and J.-S. Goo, “Evaluation of RF capacitance extraction for ultra-thin, ultra-leaky SOI MOS devices,” IEEE Electron Device Letters, vol. 28, pp. 45-47, January 2007

115. C. Yu and J. S. Yuan, “CMOS device and circuit degradations subject to HfO2 gate breakdown and transient charge trapping effect,” IEEE Trans. Electron Devices, vol. 54, pp. 59-67, January 2007

116. C. Yu and J. S. Yuan, “Electrical and temperature stress effects on class-AB power amplifier performances,” IEEE Trans. Electron Devices, vol. 54, pp. 1346-1350, June 2007

117. J. S. Yuan and J. Ma, “Evaluation of RF stress effect on class-E power amplifier power efficiency,” IEEE Trans. Electron Devices, vol. 55, pp. 430-434, January 2008

118. J. S. Yuan and L. Jiang, “Evaluation of hot-electron effect on LDMOS device and circuit performances,” IEEE Trans. Electron Devices, vol. 55, pp. 1519-1523, June 2008

119. J. S. Yuan and H. Tang, “CMOS RF design for reliability using adaptive gate-source biasing,” IEEE Trans. Electron Devices, pp. 2348-2353, September 2008

120. J. S. Yuan and C. Yu, “HfO2 gate breakdown and channel hot electron effect on MOSFET third-order intermodulation,” IEEE Trans. Electron Devices, pp. 2790-2794, October 2008

121. X. Liu, J. S. Yuan, and J. J. Liou, “InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability, Microelectronics Reliability, pp. 1212-1215, October 2008

122. W. Kuang, L. Cao, C. Yu, and J. S. Yuan, “PMOS breakdown effects on digital circuits - modeling and analysis,” Microelectronics Reliability, pp. 1597-1600, October 2008

123. S. Sun, W. Zhou, J. Xu, J. S. Yuan, and Z. Shen, “Investigation of power MOSFET with strained SiGe channel,” Electronchemical Transactions, pp. 135-140, 2009.

124. X. Liu, J. S. Yuan, and J. J. Liou, “Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance," Microelectronics Reliability, pp. 365-369, March 2010

125. W. Kuang, P. Zhao, J. S. Yuan, and R. DeMara, “Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits,” IEEE Trans. Very Large Scale Integrated Systems, pp. 410-422, March 2010

126. J. S. Yuan and J. Ma, “Voltage stress effect on class-AB power amplifier and sample-hold circuit,” Microelectronics Reliability, vol. 50, issue 6, pp. 801-806, June 2010

127. J. S. Yuan, J. Ma, W. K. Yeh, and C. W. Hsu, “Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances,” Microelectronics Reliability, pp. 807-812, June 2010

128. J. Steighner, J. S. Yuan, and Y. Liu, “Simulation and analysis of InGaAs power MOSFET performances and reliability,” IEEE Trans. Electron Devices, pp. 180-189, January 2011

129. Y. Liu and J. S. Yuan, “CMOS RF power amplifier variability and reliability resilient biasing design and analysis,” IEEE Trans. Electron Devices, pp. 540-546, February 2011

130. Y. T. Chen, K. M. Chen, W. K. Yeh, J. S. Yuan, and F. S. Yeh, “Impact of SOI thickness on FUSI-gate CESL CMOS performance and reliability,” IEEE Trans. Device and Materials Reliability, pp. 44-49, March 2011

131. S. Sun, J. S. Yuan, and Z. Shen, “Performance of trench power MOSFET with strained Si/SiGe multil-layer channel,” IEEE Trans. Electron Devices, pp. 1517-1522, May 2011

132. J. S. Yuan, W.-K. Yeh, S. Chen, and C.-W. Hsu, “NBTI reliability on high-k metal-gate SiGe transistor and circuit performances,” Microelectronics Reliability, vol. 51, pp. 914-918, May 2011

133. J. Steighner and J. S. Yuan, “The effect of SOA enhancement on device ruggedness under UIS for the LDMOSFET,” IEEE Trans. Device and Materials Reliability, pp. 254-262, June 2011

134. K. Kutty, J. S. Yuan, and S. Chen, “Evaluation of gate oxide breakdown effect on cascode class E power amplifier performance,” Microelectronics Reliability, pp. 1302-1308, August 2011

135. S. Chen and J. S. Yuan, “Adaptive gate bias for power amplifier temperature compensation,” IEEE Trans. Device and Materials Reliability, pp. 442-449, September 2011

136. Y. Liu and J. S. Yuan, “CMOS RF low-noise amplifier design for variability and reliability,” IEEE Trans. Device and Materials Reliability, pp. 450-457, September 2011

137. X. Liu, J. S. Yuan, and J. J. Liou, “Thermal reliability of VCO using InGaP/GaAs HBTs,” Microelectronics Reliability, vol. 51, pp. 2147-2152 , 2011

138. B. Yang, J. S. Yuan, and Z. Shen, “Evaluation of lateral power MOSFETs in synchronous buck converter using mixed-mode device and circuit simulation,” IEEE Trans. Electron Devices, pp. 404-410, November 2011

139. J. S. Yuan, H. D. Yen, S. Y. Chen, R. L. Wang, G. W. Huang, Y. Z. Juang, C. H. Tu, W. K. Yeh, and J. Ma, “Experimental verification of RF stress effect on cascode class E PA performance and reliability,” IEEE Trans. Device and Materials Reliability, pp. 369-375, June 2012

140. Y. Zhang and J. S. Yuan, “CMOS transistor amplifier temperature compensation: modeling and analysis,” IEEE Trans. Device and Materials Reliability, pp. 376-381, June 2012

141. J. S. Yuan and S. Chen, “A simulation study of Colpitts oscillator reliability and variability,” IEEE Trans. Device and Materials Reliability, pp. 576-581, September 2012

142. H. D. Yen, J. S. Yuan, R. L. Wang, G. W. Huang, W. K. Yeh, and F. S. Huang, “RF stress effects on CMOS LC-loaded VCO reliability evaluated by experiments,” Microelectronics Reliability, pp. 2655-2659, November 2012

143. J. Steighner and J. S. Yuan, “Examination of hot carrier effects of the AlGaAs/InGaAs pHEMT through device simulation,” Microelectronics Reliability, pp. 2932-2940, December 2012

144. J. S. Yuan and E. Kritchanchai, “Evaluation of electrical stress effect on class F power amplifier by simulation,” Advances in Microelectronic Engineering, pp. 1-8, January 2013

145. S. L. Jang, J. S. Yuan, S. D. Yen, E. Kritchanchai, and G. W. Huang, “Experimental evaluation of hot electron reliability on differential Clapp-VCO,” Microelectronics Reliability, pp. 254-258, February 2013

146. J. S. Yuan and E. Kritchanchai, “Power amplifier resilient design for process, voltage, and temperature variations,” Microelectronics Reliability, pp. 856-860, June 2013

147. J. S. Yuan, Y. Wang, J. Steighner, H.-D. Yen, S.-L. Jang, G.-W. Huang, and W.-K. Yeh, “Reliability analysis of pHEMT power amplifier with an on-chip linearizer,” Microelectronics Reliability, pp. 878-884, June 2013

148. J. S. Yuan, C. L. Lin, W. K. Yeh, and C. Xiao, “Hot electron effect on FinFET RF circuit reliability,” Advances in Microelectronic Engineering, pp. 1-6, January 2014

149. J. S. Yuan and S. Chen, “Power amplifier resilient design for process and temperature variations using an on-chip PLL sensing signal,” Microelectronics Reliability, pp. 167-171, January 2014

150. J. S. Yuan, Y. Xu, S. D. Yen, Y. Bi, and G. W. Hwang, “Hot carrier injection stress effect on 65nm LNA at 70 GHz,” IEEE Trans. Device and Materials Reliability, pp. 931-934, September 2014

151. J. S. Yuan and Y. Bi, “Process and temperature robust voltage multiplier design for RF energy harvesting,” Microelectronics Reliability, pp. 107-113, January 2015

152. W. K. Yeh, C.-L. Lin, T.-H. Chou, K. Wu, and J. S. Yuan, “The impact of junction doping distribution on device performance variability and reliability for fully depleted silicon on insulator with thin BOX layer MOSFETs,” IEEE Trans. Nanotechnology, pp. 330-337, March 2015

153. Y. Bi, J. S. Yuan, and Y. Jin, “Beyond the interconnections: Split manufacturing in RF designs,” Electronics, pp. 541-564, August 2015

154. Y. C. Liu, J. S. Yuan, and E. Kritchanchai, “An implantable cardiovascular pressure monitoring system with on-chip antenna and RF energy harvesting,” J. Systemics, Cybernetics and Informatics, Volume 13 - Number 4, pp. 1-6, 2015

155. J. S. Yuan, Y.-C. Liu, and U. Khan, “Implantable biomedical signal monitoring using RF energy harvesting & on-chip antenna,” J. Systemics, Cybernetics and Informatics, Volume 13 - Number 5, pp. 1-6, 2015

156. E. Kritchanchai and J. S. Yuan, “CMOS voltage-controlled oscillator resilient design for wireless communication applications,” J. Systemics, Cybernetics and Informatics, Volume 13 - Number 5, pp. 76-80, 2015

157. K. Padmanabhan, M. Bobde, L. Guan, and J. S. Yuan, “Robust trench buried guard ring based termination for charge balanced devices,” IEEE Trans. Device and Materials Reliability, pp. 69-73, March 2016

158. S. D. Yen, J. S. Yuan, G. W. Huang, W. K. Yeh, and F. S. Huang, “Reliability performance of a 70 GHz mixer in 65nm technology,” IEEE Trans. Device and Materials Reliability, pp. 101-104, March 2016

159. Y. Bi, K. Shamsi, J. S. Yuan, P.-E. Gaillardon, G. de Micheli, X. Yin, X. Hu, M. Niemier, and Y. Jin, “Emerging technology based design of primitives for hardware security,” ACM Journal on Emerging Technologies in Computing Systems, Volume 13 Issue 1, pp. 3:1-3:19, April 2016

160. J. Lin and J. S. Yuan, “Ultra-low power successive approximation analog-to-digital converter using emerging tunnel field effect transistor technology,” Journal of Low Power Electronics, Vol. 12, No. 3, pp. 218-226, September 2016

161. Q. Alasad, Y. Bi, and J. S. Yuan, "E2LEMI: Energy-efficient logic encryption using multiplexer insertion," Electronics, 6, 16, pp. 1-20, February 2017

162. S. Taheri and J. S. Yuan, “Security analysis of tunnel field-effect transistor for low power hardware,” Int. Journal of Computer Science and Information Technologies, vol. 8(2), pp. 271-275, April 2017

163. S. Taheri and J. S. Yuan, “Security protection for magnetic tunnel junction,” Int. Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering, vol. 5, issue 4, April 2017

164. S. Taheri, J. Lin, and J. S. Yuan, “Security interrogation and defense for SAR analog to digital converter,” Electronics, 6, 48, pp. 1-17, June 2017

165. Y. Bi, K. Shamsi, J. S. Yuan, Y. Jin, X. Hu, and M. Niemier, “Tunnel FET current mode logic for DPA-resilient circuit designs,” IEEE Trans. Emerging Technologies in Computing, vol. 5, No. 3, pp. 340-352, July-Sept. 2017

166. S. Taheri and J. S. Yuan, “Mixed-signal hardware security: Attacks and countermeasures for Delta-Sigma ADC,” Electronics, 6(3), 60, pp. 1-21, August 2017, doi: 10.3390

167. J. Lin and J. S. Yuan, “12-bit ultra-low voltage noise shaping SAR ADC using emerging TFETs,” Journal of Low Power Electronics, Vol. 13, No. 3, pp. 497-510(14), September 2017

168. J. S. Yuan, J. Lin, Q. Alasad, and S. Taheri, “Ultra-low power design and hardware security using emerging technologies for internet of things,” Electronics, 6(3), 67, pp. 1-54, September 2017, doi: 10.3390

169. Q. Alasad, J. S. Yuan, and Y. Bi, “Logic locking using CMOS and emerging SiNW FETs,” Electronics, 6(3), 69, pp. 1-19, September 2017, doi: 10.3390

170. A. Oberai and J. S. Yuan, Smart E-beam for defect identification & analysis in the nanoscale technology nodes: Technical perspectives,” Electronics, 6(4), 87, pp. 1-28, October 2017, doi: 10.3390

171. S. Taheri and J. S. Yuan, “A Cross-layer biometric recognition system for mobile IoT devices,” Electronics, 7, 26, pp. 1-17, February 2018, doi: 10.3390

172. A. Oberai and J. S. Yuan, “Efficient fault localization and failure analysis techniques for improving IC yield,” Electronics, 7, 28, pp. 1-22, February 2018, doi: 10.3390

173. A. Salih and J. S. Yuan, “Evaluation of LDMOS figure of merit using device simulation,” Electronics, 7, 60, pp. 1-10, April 2018, doi: 10.3390

174. A. Binder, J. S. Yuan, B. Krishnan, and P. Shea, Fabless design approach for lateral optimization of low voltage GaN power HEMTs, Superlattices and Microstructures, 121, pp. 92-106, July 2018

175. M. Salem, S. Taheri, and J. S. Yuan, “An experimental evaluation of fault diagnosis from imbalanced and incomplete data for smart semiconductor manufacturing,” Big Data and Cognitive Computing, 2, 30, pp1-24, September 2018, doi: 10.3390

176. J. Lin and J. S. Yuan, “Analysis and simulation of capacitor-less ReRAM-based stochastic neurons for in-memory spiking neural network,” IEEE Trans. Biomedical Circuits and Systems, vol. 12, no. 5, pp. 1004-1017, October 2018

177. S. Taheri, M. Salem, and J. S. Yuan, “Leveraging image representation of network traffic data and transfer learning in botnet detection,” Big Data and Cognitive Computing, 2, 37, pp. 1-16, November 2018, doi: 10.3390

178. M. Salem, S. Taheri, and J. S. Yuan, “Utilizing transfer learning and homomorphic encryption in a privacy preserving and secure biometric recognition system,” Computers, 8, 3, pp. 1-24, December 2018, doi:10.3390

179. A. Binder, S. Khan, W. Yang, J. S. Yuan, B. Krishnan, and P. Shea, “Effects of heterostructure design on performance for low voltage GaN power HEMTs,” ECS Journal of Solid State Science and Technology, 8(2), pp. Q15-Q23, February 2019

180. W. Yang, J. S. Yuan, B. Krishnan, and P. Shea, “Characterization of deep and shallow traps in GaN HEMT using multi-frequency C-V measurement and pulse-mode voltage stress,” IEEE Transactions on Device and Materials Reliability, pp. 350-357, June 2019

181. S. Taheri, M. Salem, and J. S. Yuan, “RezorNet: Adversarial training and noise training on a deep neural network fooled by a shallow neural network,” Big Data and Cognitive Computing, 3, 43, pp. 1-17, July 2019, doi: 10.3390/bdcc3030043

182. A. Binder, J. S. Yuan, B. Krishnan, P. Shea, and W. -K. Yeh, “Trap induced negative differential conductance and back-gated charge redistribution in AlGaN/GaN power devices,” Microelectronics Reliability, 102, 2019, 113495, doi: 10.1016

183. A. K. Arshadi, M. Salem, J. Collins, J.-S. Yuan, and D. Charabarti, “DeepMalaria: Artificial intelligence driven discovery of potent antiplasmodials,” Frontiers in Pharmacology, doi: 10.3389/fphar.2019.01526

184. J. Lin and J. S. Yuan, “A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons,” Neurocomputing, 375, pp. 102-112, 2020

185. W. Yang and J. S. Yuan, “Experimental investigation of buffer traps physical mechanisms on the gate charge of GaN-on-Si devices under various substrate biases,” Applied Physics Letters, 116, 083501, February 2020, doi: 10.1063/1.512487

186. S. Taheri, A. Khormali, M. Salem, and J. S. Yuan, “Developing a robust defensive system against adversarial examples using generative adversarial networks,” Big Data and Cognitive Computing, 4, 11, pp. 1-14, May 2020, doi.org/10.3390/bdcc4020011

187. Q. Alasad, J. S. Yuan, and P. Subramanyan, “Strong logic obfuscation with low overhead against IC reverse engineering attacks,” ACM Trans. Design Automation of Electronic Systems, vol. 25, no. 4, June 2020, doi: 10.1145/3398012

188. M. Salem, A. Khormali, A. Arshadi, J. Webb, and J. S. Yuan, “TranScreen: Transfer learning on graph-based anti-cancer virtual screening model,” Big Data and Cognitive Computing, 4(3), 16, pp. 1-20, June 2020, doi.org/10.3390/bdcc4030016

189. A. K. Arshadi, J. Webb, M. Salem, E. Cruz, S. Calad-Thomas, N. Ghadirian, J. Collins, E. Diez-Cecillia, B. Kelly, H. Goodarzi, and J. S. Yuan, “Artificial intelligence for COVID-19 drug discovery and vaccine development,” Frontiers in Artificial Intelligence, August 2020, doi: 10.3389/frai.2020.00065

190. Q. Alasad, J. Lin, J. S. Yuan, A. Awad, and D. Fang, “Resilient and secure hardware devices using ASL,” Journal on Emerging Technologies in Computing Systems, vol. 17, no. 2, January 2021, doi.org/10.1145/3429982

191. A. Tamir, E. Watson, B. Willetee, Q. Hasan, and J. S. Yuan, “Crime prediction and forecasting using machine learning algorithms,” International Journal of Computer Science and Information Technologies, vol. 12, issue 2, pp. 26-33, April 2021, ISSN 0975-9646

192. W. Yang and J. S. Yuan, “Substrate enhanced trap effects on time-dependent dielectric breakdown of GaN MIS-HEMTS,” IEEE Trans. Electron Devices, vol. 68, issue. 5, pp. 2233- 2239, May 2021, doi: 10.1109/TED.2021.3067615

193. A. Mahdavian, A. Shojaei, M. Salem, J. S. Yuan, and A. A. Oloufa, “Data-driven predictive modeling of highway construction cost items,” Journal of Construction Engineering and Management,147, 3 (2021): 04020180

194. A. Tamir, M. Salem, J. Lin, Q. Alasad, and J. S. Yuan, “Multi-tier 3D IC physical design with analytical quadratic partitioning algorithm using 2D P&R tool, Electronics, 10(16), 1930, August 2021, doi.org/10.3390/electronics10161930

195. A. Khormali and J. S. Yuan, “ADD: Attention-based deepfake detection approach,” Big Data and Cognitive Computing, 5(4), 49, September 2021 doi.org/10.3390/bdcc5040049

196. W. Yang, N. Stoll, and J. S. Yuan, “ESD stress effect on failure mechanisms in GaN-on-Si power device, IEEE Trans. Materials and Device Reliability, vol. 21, issue 4, pp. 479-485, December 2021, doi: 10.1109/TDMR.2021.3108761

197. A. Mahdavin, A. Shojaei, M. Salem, H. Laman, J. S. Yuan, and A. Oloufa, “Automatic machine learning pipeline for traffic count prediction,” Modelling 2021, 2(4), 482-513, doi.org/10.3390/modelling20400026

198. A. K. Arshadi, M. Salem, A. Firouzbakht, and J. S. Yuan, “MolData, A molecular benchmark for disease and target based machine learning,” Journal of Cheminformatics, BMC Part of Springer Nature, 14, Article number 10, March 2022, https://doi.org/10.1186/s13321-022-00590-y

199. A. Khormali and J. S. Yuan, “DFDT: An end-to-end deepfake detection framework using vision transformer,” Applied Sciences, 12(6), 2953, March 2022, https://doi.org/10.3390/app12062953

200. W. Yang and J. S. Yuan, “Negative-bias temperature instability of p-GaN gate GaN-on-Si power devices,” IEEE Trans. Device and Materials Reliability, accepted for publication, March 2022, doi: 10.1109/TDMR.2022.3160396