CONFERENCE PAPERS

1. J. G. Fossum, H. G. Jeong, J. S. Yuan, and W. R. Eisenstadt, “Steady-state and transient SPICE2 modeling of high current phenomena in ECL BJT's,” SRC Topical Research Conference, Tempe, AZ, April 1986

2. M. S. Jo, D. E. Burk, J. S. Yuan, and W. R. Eisenstadt, “Improved SLICE simulation of digital bipolar transistors using s-parameter data,” IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, September 1986

3. J. S. Yuan, W. R. Eisenstadt, and J. G. Fossum, “Multidimensional currents in advanced bipolar transistors,” SRC Topical Research Conference: Bipolar Device Modeling, Gainesville, FL, May 1987

4. J. S. Yuan and W. R. Eisenstadt, “S-parameter measurement prediction for bipolar transistors using a physical device simulator,” IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, May 1987

5. J. J. Liou and J. S. Yuan, “Compact bipolar transistors model for one-dimensional circuit simulation,” IEEE Southeast Conference, April 1988

6. J. S. Yuan and W. R. Eisenstadt, “Two-dimensional modeling of advanced bipolar transistors and interconnects for mixed-mode circuit simulation,” SRC Bipolar Review Meeting and BiCMOS Roadmap, Gainesville, FL, April 1988

7. J. J. Liou, J. S. Yuan, and W. R. Eisenstadt, “Two-dimensional emitter-base junction capacitance for bipolar circuit simulation,” Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, NUPAD-II, San Diego, CA, May 1988

8. J. S. Yuan and W. R. Eisenstadt, “Interconnect circuit model development based on 2-D device simulation,” Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, NUPAD-II, San Diego, CA, May 1988

9. J. J. Liou and J. S. Yuan, “An accurate bipolar transistor model for low temperature circuit simulation,” IEEE Custom Integrated Circuits Conference, May 1989

10. J. S. Yuan and J. J. Liou, “An improved bipolar small-signal model for circuit simulation,” Florida Microelectronics Conference," May 1990

11. J. S. Yuan and J. J. Liou, “Parasitic capacitance effects of the multilevel interconnects in DRAM circuits,” IEEE VLSI Multilevel Interconnection Conference, Santa Clara, CA, June 1990

12. J. S. Yuan and J. J. Liou, “Interconnect noise analysis for megabit DRAMs,” IEEE VLSI Multilevel Interconnection Conference, Santa Clara, CA, June 1990

13. J. J. Liou, W. Drafts, and J. S. Yuan, “Modeling the heterojunction bipolar transistor for integrated circuit simulation,” 1990 IEEE Biennial University/Government/Industry Microelectronics Symposium, June 1990

14. J. S. Yuan and J. J. Liou, “Array noise analysis for high-density dynamic RAM design,” 33rd Midwest Symposium on Circuits and Systems, Calgary, Canada, August 1990

15. J. S. Yuan and J. J. Liou, “An optimal latching waveform design for dynamic sense amplifiers,” 33rd Midwest Symposium on Circuits and Systems, Calgary, Canada, August 1990

16. J. S. Yuan, J. J. Liou, and D. M. Wu, “Testing the impact of process defects on ECL power-delay performance,” 1991 IEEE VLSI Test Symposium, Atlantic, NJ, April 1991

17. W. W. Wong, J. J. Liou, J. S. Yuan, and D. M. Wu, “Statistical sensitivity simulation of MOSFET integrated circuits,” 1991 IEEE VLSI Test Symposium, Atlantic, NJ, April 1991

18. J. S. Yuan and S. Seshan, “BiCMOS gate delay analysis including high current transients,” 22nd Annual Pittsburgh Conference on Modeling and Simulation, May 1991

19. J. S. Yuan and H. Pham, “BiCMOS gate delay analysis including temperature effect and high current transients,” IEEE Southeastcon '92, April 1992

20. J. S. Yuan, J. Blanchard, and C. Panchapakesan, “Heterojunction bipolar transistor performance and modeling for communication circuit applications,” 23rd Annual Pittsburgh Conference on Modeling and Simulation, May 1992

21. J. S. Yuan, “Reliable multi-megabit DRAM design for VLSI manufacturing,” the Fourth Annual Florida Microelectronics Conference, Tampa, FL, May 7-8, 1992

22. J. S. Yuan, C. S. Yeh, and B. Gadepally, "Effect of base profile on forward transit time of bipolar transistors in BiCMOS circuits," 1993 IEEE Biennial University/Government/Industry Microelectronics Symposium, Research Triangle Park, NC, May 18-20, 1993

23. J. S. Yuan, “Thermal and reverse base current effects on heterojunction bipolar transistors and circuits,” SPIE's International Symposium on Optoelectronics for Information and Microwave Systems, Los Angeles, CA, January 1994

24. J. S. Yuan, “An integral Gummel relation for single- and double-heterojunction graded-base HBT's,” SPIE's International Symposium on Optoelectronics for Information and Microwave Systems, Los Angeles, CA, January 1994

25. J. S. Yuan and J. Lyons, “Design and modeling of p-i-n photodetectors using MEDICI,” SPIE's International Symposium on Optoelectronics for Information and Microwave Systems, Los Angeles, CA, January 1994

26. A. M. Phones, J. S. Yuan, C. S. Yeh, and B. Gadepally, “Radiation and hot electron effects on BiCMOS switching,” IEEE Southcon ‘94, Orlando, FL, March 1994

27. C. Panchapakesan and J. S. Yuan, “Evaluation of Aluminum mole fraction for controlled thermal behavior of AlGaAs/GaAs HBT,” IEEE Southcon ‘94, Orlando, FL, March 1994

28. A. M. Phones, J. S. Yuan, Y. Dai, C. S. Yeh, and B. Gadepally, “Effects of scaling and radiation on BiCMOS switching,” 1994 International Electron Devices and Materials Symposium, Hsinchu, Taiwan, July 13-15, 1994

29. D. M. Wu, J. S. Yuan, M. DeBrino, and N. Ngo, “Fault modeling and verification of multi-million transistor VLSI circuits,” IEEE Westcon ‘95, San Francisco, CA, November 1995

30. J. S. Yuan and J. Ning, “Analysis of abrupt and linearly-graded HBT’s with or without setback layer,” 1st IEEE International Caracas Conference on Devices, Circuits, and Systems, Caracas, Venezuela, December 1995

31. Y. Gu and J. S. Yuan, “Oxide thickness effects on hot-carrier-induced degradation in n-MOSFETs,” IEEE Southeastcon ‘96, Tampa, FL, April 1996

32. J. Ning, J. S. Yuan, and R. Sinanan-Singh, “High performance heterojunction bipolar transistors with non-uniform doping profiles,” IEEE Southcon ‘96, Orlando, FL, June 1996

33. Y. Dai, J. S. Yuan, J. Song, and P. Campbell, “Scalable bipolar transistor model including quasi-saturation effect for BiCMOS applications,” IEEE Southcon ‘96, Orlando, FL, June 1996

34. Y. Gu and J. S. Yuan, “Oxide and substrate thickness effects on scaled MOS Transistors,” IEEE Southcon ‘96, Orlando, FL, June 1996

35. A. M. Phones, H. You, R. Mendel, and J. S. Yuan, “Behavioral modeling of a phase-locked-loop,” IEEE Southcon ‘96, Orlando, FL, June 1996

36. Y. Dai, J. S. Yuan, A. Phones, C.-S. Yeh, and K. Hwang, “Scalable bipolar model for BiCMOS and bipolar circuits,” 3rd International Conference on Electronics, Circuits, and Systems, Rhodes, Greece, October 13-16, 1996

37. J. Song, J. S. Yuan, F. Schwierz, and D. Schipanski, “Effects of Ge profiles on base transit time and base resistance of SiGe HBT’s,” 3rd International Conference on Electronics, Circuits, and Systems, Rhodes, Greece, October 13-16, 1996

38. Y. Gu and J. S. Yuan, “Gate Oxide thickness effects on hot-electron-induced degradation in n-MOSFET’s,” 1996 International Electron Devices and Materials Symposium, Hsin Chu, Taiwan, December 16-20, 1996

39. Y. Dai, J. S. Yuan, and C.-S. Yeh, “Scalable quasi-saturation BJT model for circuit simulation,” 1996 International Electron Devices and Materials Symposium, Hsin Chu, Taiwan, December 16-20, 1996

40. J. Song and J. S. Yuan, “Effects of Ge profiles on the performance of SiGe HBT’s,” 1996 International Electron Devices and Materials Symposium, Hsin Chu, Taiwan, December 16-20, 1996

41. Y. Dai and J. S. Yuan, “Current-dependent collector resistance of the BJT,” IASTED International Conference on Applied Modelling and Simulation, Banff, Canada, July 27 - August 1, 1997

42. J. S. Yuan and J. Song, “Early voltage of SiGe heterojunction bipolar transistors,” 1997 IEEE Hong Kong Electron Devices Meeting, Hong Kong, August 30, 1997

43. D. M. Nuernbergk, H. Forster, F. Schwierz, J. S. Yuan, and G. Paasch, “Comparison of Monte Carlo, energy transport, and drift diffusion simulation for the Si/SiGe/Si HBT,” High Performance Electron Devices for Microwave and Optoelectronic Applications, London, UK, November 24-25, 1997

44. D. M. Nuernbergk, H. Forster, F. Schwierz, J. S. Yuan, and G. Paasch, “On the temperature behavior of SiGe heterojunction bipolar transistors: Comparison between experimental data and simulation results,” 2nd IEEE International Caracas Conference on Devices, Circuits, and Systems, Magarita Island, Venezuela, March 1998

45. K. L. Davis and J. S. Yuan, “Impact of technology on low-voltage CMOS and BiCMOS switching delay,” Southeastcon’98, Orlando, Florida, April 1998

46. J. Song and J. S. Yuan, “Modeling the base-collector heterojunction barrier effect at high current densities of SiGe HBTs,” Southeastcon’98, Orlando, Florida, April 1998

47. M. M. Mahin, J. S. Yuan, A. Whittaker, M. Chian, and K. Ports, “Substrate noise coupling in mixed-signal ICs,” Southeastcon’98, Orlando, Florida, April 1998

48. J. S. Yuan and J. Song, “Modeling the base-collector heterojunction barrier effect at high current densities of SiGe HBTs,” Hong Kong Electron Device Meeting, Hong Kong, August 29, 1998

49. J. S. Yuan, invited paper, “Overview of SiGe Technology Modeling and Application,” First International Symposium on Quality of Electronic Design, San Jose, California, March 20-22, 2000

50. S. Li, K. Pan, J. S. Yuan, A. J. Vigil, and A. Berg, “Adaptive Reed-Solomon coding for wireless ATM communications,” IEEE Southeastcon, Nashville, Tennessee, April 7-9, 2000

51. J. Zhang, J.S. Yuan, Y. Ma, and A. Oates, “Design optimization of stacked gate oxides with easy evaluation of gate leakage in deep submicron MOSFET,” 58th Annual Device Research Conference, Denver, Colorado, June 19-21, 2000

52. L. Qiang and J. S. Yuan, “CMOS RF low-noise amplifier design for wireless communication,” Midwest Symposium for Circuits and Systems 2000, Lansing, Michigan, August 8-11, 2000

53. X. Duan, W. Wu, and J. S. Yuan, “Hole detrapping effect on gate oxide breakdown under ac and dc stresses"”, International Integrated Reliability Workshop, Stanford Sierra Camp, Lake Tahoe, California, October 23-26, 2000

54. J. Zhang, J. S. Yuan, Y. Ma, and T. Oates, “Surface roughness effects on I-V and C-V characteristics of ultra-thin gate MOS transistors,” International Integrated Reliability Workshop, Stanford Sierra Camp, Lake Tahoe, California, October 23-26, 2000

55. W. Wu, S. H. Kang, J. S. Yuan, and A. S. Oates, “Electromigration performance for Al/SiO2, Cu/SiO2, and Cu/low-k interconnect systems with Joule heating effect,” International Integrated Reliability Workshop, Stanford Sierra Camp, Lake Tahoe, California, October 23-26 2000

56. W. Li, J. S. Yuan, S. Chetlur, J. Zhou, and A. S. Oates, “An improved substrate current model for deep submicron CMOS transistors,” International Integrated Reliability Workshop, Stanford Sierra Camp, Lake Tahoe, California, October 23-26, 2000

57. W. Kuang, J.S. Yuan, R. DeMara, D. Ferguson, and M. Hagedorn, “A delay-insensitive FIR filter for DSP applications,” 9th Annual NASA Symposium on VLSI Design, Albuquerque, New Mexico, November 8-9, 2000

58. N. Weng, J.S. Yuan, R. DeMara, D. Ferguson, and M. Hagedorn, “Glitch power reduction for low power IC design,” 9th Annual NASA Symposium on VLSI Design, Albuquerque, New Mexico, November 8-9, 2000

59. Wei Li, Qiang Li, J. S. Yuan, J. McConkey, Y. Chen, S. Chetlur, J. Zhou, and A.Oates, “Hot-carrier-induced circuit degradation for 0.18 m CMOS technologies,” International Symposium for Quality Electron Design, San Jose, California, March 26-28, 2001

60. Q. Li, J. Zhang, W. Li, J. S. Yuan, Y. Chen, and A. Oates, “RF circuit performance degradation due to soft breakdown and hot carrier effect in 0.18 m CMOS Technology,” 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Phoenix, Arizona, May 20-22, 2001

61. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Speedup of delay-insensitive digital systems using NULL cycle reduction,” 10th International Workshop on Logic and Synthesis, pp. 185-189, Lake Tahoe, California, June 2001

62. Q. Li, J. Zhang, W. Li, and J. S. Yuan, “CMOS RF mixer non-linearity design,” Midwest Symposium for Circuits and Systems 2001, Fairborn, Ohio, August 14-17, 2001

63. Q. Li, J. Zhang, and J. S. Yuan, “Soft Breakdown and Hot Carrier Reliability for CMOS RF Mixers,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Seattle, Washington, June 2-4, 2002

64. E. Xiao and J. S. Yuan, “Effects of hot carrier stress and oxide soft breakdown on VCO performance,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Seattle, Washington, June 2-4, 2002

65. L. Yang, J. S. Yuan, and M. Hagedorn, “Analyzing the simultaneous switching noise due to internal gate switching,” 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 4-7, 2002

66. E. Xiao, J. S. Yuan, and H. Yang, “RF circuit performance degradation due to hot carrier effect and soft breakdown, “45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 4-7, 2002

67. J. Di, J. S. Yuan, and M. Hagedorn, “Energy-aware multiplier design in multi-rail encoding logic,” 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 4-7, 2002

68. J. Di, J. S. Yuan, and M. Hagedorn, “Switching activity modelling of multi-rail speed-independent circuits – a probabilistic approach,” 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 4-7, 2002

69. L. Yang, J. S. Yuan, and M. Hagedorn, “Modeling the output waveform of CMOS gate with feedback effect,” 9th International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, September 15-18, 2002

70. W. Kuang and J. S. Yuan, “Low power operation using self-timed circuits and ultra-low supply voltage,” International Conference on Microelectronics, Beirut, Lebanon, December 11-13, 2002

71. E. Xiao, J. S. Yuan, and H. Yang, “Hot carrier and soft breakdown reliability for RF circuits,” International Conference on Semiconductor Electronics, Penang, Malaysis, December 19-21, 2002

72. W. Kuang and J. S. Yuan, “Soft digital signal processing using self-timed circuits,” International Conference on Semiconductor Electronics, Penang, Malaysis, December 19-21, 2002

73. W. Kuang and J. S. Yuan, “An adaptive supply-voltage scheme for low power self-timed CMOS digital design”, 16th International Conference on VLSI Design, New Delhi, India, January 4-8, 2003

74. W. Kuang, J. S. Yuan, and A. Ejnioui, “Supply voltages scalable system design using self-timed circuits,” IEEE Annual Symposium on VLSI, Tampa, Florida, February 20-21, 2003

75. L. Yang and J. S. Yuan, “Enhanced techniques for current balanced logic in mixed-signal ICs,” IEEE Annual Symposium on VLSI, Tampa, Florida, February 20-21, 2003

76. J. Di, J. S. Yuan, and R. DeMara, “High throughput power-aware FIR filter design based on fine-grain pipeline multipliers and adders,” IEEE Annual Symposium on VLSI, Tampa, Florida, February 20-21, 2003

77. L. Yang and J. S. Yuan, “Analyzing internal-switching induced simultaneous switching noise,” International Symposium on Quality Electronic Design, Santa Clara, California, March 24-27, 2003

78. H. Yang, J. S. Yuan, and E. Xiao, “Effect of gate oxide breakdown on RF device and circuit performance,” International Reliability Physics Symposium, Dallas, Texas, March 30–April 4, 2003

79. W. Wu, X. Duan, and J. S. Yuan, “A physical model of time-dependent dielectric breakdown in copper metallization,” International Reliability Physics Symposium, Dallas, Texas, March 30 -April 4, 2003

80. E. Xiao, J. S. Yuan, and H. Yang, “RF device and circuit reliability,” IEEE Southeastcon, Ocho Rios, Jamaica, April 4-6, 2003

81. J. Di and J. S. Yuan, “Power-aware pipelined multiplier design based on 2-dimensional pipeline gating,” Great Lake Symposium on VLSI, Washington D.C., April 28-29, 2003

82. J. Di and J. S. Yuan, “Run-time reconfigurable power-aware pipelined signed array multiplier design,” Int. Symp. Signals, Circuits and Systems, June 2003

83. L. Yang and J. S. Yuan, “Decoupling technique for CMOS strong-coupled structures,” Great Lake Symposium on VLSI, Washington D.C., April 28-29, 2003

84. E. Xiao and J. S. Yuan, “Evaluation of oscillator phase noise subject to reliability,” 2003 IEEE International Frequency Control Symposium, Tampa, Florida, May 5-7, 2003

85. A. Sadat, E. Xiao and J. S. Yuan, “Breakdown effects on MOS varactors and VCO's,” 2003 IEEE International Frequency Control Symposium, Tampa, Florida, May 5-7, 2003

86. L. Yang and J. S. Yuan, “Design of enhancement current-balanced logic for mixed-signal ICs,” IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 25-28, 2003

87. H. Yang, R. Smith, and J. S. Yuan, “Gate oxide breakdown on low noise and power amplifier performance,” 2003 Radio-Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, June 8-10, 2003

88. E. Xiao and J. S. Yuan, “RF circuit design in reliability,” 2003 Radio-Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, June 8-10, 2003

89. J. S. Yuan, Invited Paper: “CMOS RF device and circuit reliability,” 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, Orlando, Florida, November 17-18, 2003

90. Y. Liu, A. Sadat, J. S. Yuan, and H. Yang, “Soft breakdown on deep sub-micrometer RF nMOSFET performance,” 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, Orlando, Florida, November 17-18, 2003

91. C. Yu and J. S. Yuan, “Linearity and power optimization of a microwave CMOS gilbert cell mixer,” 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, Orlando, Florida, November 17-18, 2003

92. L. Yang, C. Yu, and J. S. Yuan, “Analytical analysis of static noise margin for CMOS gate with short-channel devices,” IEEE Midwest Symposium on Circuits and Systems, Cario, Egypt, December 30-31, 2003

93. A. Sadat, Y. Liu, J. S. Yuan, and H. Xie, “Soft breakdown effects on MOS switch and passive mixer,” International Reliability Physics Symposium, Phoenix, AZ, April 25-29, 2004

94. J. S. Yuan, “Education on CMOS RF device and circuit reliability,” American Association of Engineering Education - Southeast Section Annual Conference, Auburn Alabama, April 4-6, 2004

95. H. Qu, D. Fang, A. Sadat, J. S. Yuan, and H. Xie, “High-resolution integrated micro-gyroscope for space applications,” 41st Space Congress, Cape Canaveral, Florida, April 27-30, 2004

96. A. Sadat, J. S. Yuan, and H. Xie, “Integrated wireless MEMS accelerometer for physiological activity monitoring,” the 8th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, Florida July 18-21, 2004

97. Y. Liu, A. Sadat, C. Yu, and J. S. Yuan, “RF performance degradation in PMOS transistors due to hot carrier and soft breakdown effects,” IEEE Topical meeting on Silicon Monolithic Integrated Circuits in RF Systems, September 8-10, 2004

98. J. S. Yuan, E. Xiao, and A. Sadat, “Education on CMOS IC design and reliability,” International Conference on Engineering Education, Gainesville, Florida, October 16-21, 2004

99. C. Yu and J. S. Yuan, “RF reliability of MOSFETs subject to electrical stress,” 7th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, October 18-21, 2004

100. J. S. Yuan, “RF CMOS device and circuit reliability subject to electrical and temperature stress,” Microelectronic Reliability & Qualification Workshop, Manhattan Beach, CA, December 7-8, 2004

101. C. Yu and J. S. Yuan, “Evaluation of performance degradation in RFICs due to voltage stress,” The Graduate Research Forum, University of Central Florida, Orlando, Florida, March 22, 2005

102. Y. Li and J. S. Yuan, “Gate oxide breakdown on deep sub-micrometer RF nMOSFET performance,” The Graduate Research Forum, University of Central Florida, Orlando, Florida, March 22, 2005

103. J. Di and J. S. Yuan, “Energy-aware dural-rail bit-wise completion pipelined multipliers design,” IEEE Southeastcon, Fort Lauderdale, FL, April 8-10, 2005

104. C. Yu and J. S. Yuan, “RF reliability subject to dynamic voltage stress in NMOS circuits,” International Reliability Physics Symposium, San Jose, CA, April 17-21, 2005

105. E. Xiao, P. Zhu, J. S. Yuan, and C. Yu, “Analysis and modeling of LNA circuit reliability,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2005, Long Beach, CA, June 12-14, 2005

106. J. Di and J. S. Yuan, “Dynamic active-bit detection and operands exchange for designing energy-aware asynchronous multipliers,” 2005 International Multiconference in Computer Science & Computer Engineering, Las Vegas, Nevada, June 27-30, 2005

107. C. Yu, E. Xiao, and J. S. Yuan, “Voltage stress-induced hot carrier effect on SiGe HBT VCO,” European Symposium on Reliability of Electron Devices, Bordeaux, France, October 11-14, 2005

108. C. Yu, J. S. Yuan, and A. Sadat, “Dynamic-stress-induced high-frequency noise degradations in nMOSFETs,” European Symposium on Reliability of Electron Devices, Bordeaux, France, October 11-14, 2005

109. E. Xiao, P. Ghosh, C. Yu, and J. S. Yuan, "Hot carrier and soft breakdown effects on LNA performance for ultra wideband communications,” European Symposium on Reliability of Electron Devices, Bordeaux, France, October 11-14, 2005

110. C. Yu and J. S. Yuan, “Hot carrier-induced degradation on high-k transistors and low noise amplifier,” International Reliability Physics Symposium, San Jose, California, March 26-30, 2006

111. C. Yu, L. Jiang, and J. S. Yuan, “Study of performance degradations in DC-DC converter due to hot carrier stress by simulation,” European Symposium on Reliability of Electron Devices, Wuppertal, Germany, October 3-6, 2006

112. C. Yu, J. S. Yuan, and E. Xiao, “Dynamic voltage stress effects on nMOS varactor,” European Symposium on Reliability of Electron Devices, Wuppertal, Germany, October 3-6, 2006

113. L. Jiang and J. S. Yuan, “Dynamic stress effect on LDMOS RF performances,” IEEE Power Electronics Specialists Conference, Orlando, Florida, June 17-21, 2007

114. J. S. Yuan, invited paper, “HfO2 CMOS device and circuit reliability,” IEEE International Conference on Electron Devices and Solid-State Circuits, Tainan, Taiwan, December 20-22, 2007

115. X. Liu, J. S. Yuan, and J. J. Liou, “InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability,” European Symposium on Reliability of Electron Devices, Maastricht, Netherlands, September 29-October 2, 2008

116. J. S. Yuan and J. Ma, Invited paper, “Gate oxide breakdown location effect on power amplifier and mixed-signal circuits,” 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, October 20-23, 2008

117. X. Liu, J. S. Yuan, and J. J. Liou, “Study of electrothermal effect on RF performance of InGaP/GaAs heterojunction bipolar transistor-based low-noise amplifier,” IEEE Compound Semiconductor IC Symposium, Monterey, California, October 12-15, 2008

118. W. Kuang, L. Cao, C. Yu, and J. S. Yuan, “PMOS breakdown effects on digital circuits - modeling and analysis,” European Symposium on Reliability of Electron Devices, Maastricht, Netherlands, September 29-October 2, 2008

119. S. Sun, W. Zhou, L. Yan, J. Xu, J. S. Yuan, and Z. Shen, “Investigation of power MOSFET with strained SiGe channel,” International Semiconductor Technology Conference, Shanghai, China, March 17-19, 2009

120. B. Yang, J. S. Yuan, Z. Shen, “Reliability and failure mechanisms of lateral MOSFETs in synchronous DC-DC buck converter,” 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, Suzhou, China, July 6-10, 2009

121. J. S. Yuan, J. Ma, C. W. Hsu, and W. K. Yeh, “Hot electron stress effect on dual-band power amplifier and integrated mixer-LNA design for reliability,” 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, Suzhou, China, July 6-10, 2009

122. Y. Liu, J. S. Yuan, and J. Steighner, “InGaAs LDMOS power semiconductor device performances,” 8th International Conference on Power Electronics and Drive Systems, Taipei, Taiwan, November 2-5, 2009

123. W. K. Yeh, C. C. Wang, C. W. Hsu, Y. K. Fang, S. M. We, C. C. Ou, L. Lin, K. J. Gan, C. J. Weng, P. Y. Chen, J. S. Yuan, and J. J. Liou, “Impact of oxide trap charge on performance of strained fully depleted SOI metal-gate MOSFET,” IEEE International Electron Devices and Solid-State Circuits Conference, Xi’an, China, November 2009, pp. 197-200

124. G. Varquez Ramos and J. S. Yuan, “Development of a novel wireless electric power transfer system for space applications,” 15th World Multiconference on Systemics, Cybemetics, and Informatics, Orlando, Florida, July 19th - 22nd, 2011

125. Y. Wang and J. S. Yuan, “An integrated CMOS high power amplifier using power combining technique,” IEEE Southeastcon, Orlando, Florida, March 15-18, 2012

126. G. Varquez Ramos and J. S. Yuan, “FEM simulation to characterize wireless electric power transfer elements,” IEEE Southeastcon, Orlando, Florida, March 15-18, 2012

127. G. Varquez Ramos and J. S. Yuan, “Radiated emissions testing of space wireless electric power transfer systems,” IEEE Southeastcon, Orlando, Florida, March 15-18, 2012

128. Invited talk, J. S. Yuan, “RF power amplifier design for reliability and variability,” 21st Symposium on Nano Device Technology, Hsin-Chu, Taiwan, May 1-2, 2014

129. Y. Bi, P. Gaillardon, X. Hu, M. Niemier, J. S. Yuan, and Y. Jin, “Leveraging emerging technology for hardware security – Case study on silicon nanowire FET and graphene SymFETs,” 23rd Asian Test Symposium, Hangzhou, China, November 16-19, 2014

130. G. Brussenskily and J. S. Yuan, “Robust PUF circuit design against temperature variations and aging effect,” International Conference on Security and Management, Las Vegas, Nevada, July 27-20, 2015

131. Y. Bi, J. S. Yuan, and Y. Jin, “Split manufacturing in radio frequency designs,” International Conference on Security and Management, Las Vegas, July 27-20, 2015

132. J. S. Yuan, Y. C. Liu, and U. Khan, “Implantable biomedical signal monitoring using RF energy harvesting and on-chip antenna,” 19th World Multiconference on Systemics, Cybernetics, and Informatics, Orlando, Florida, July 12-15, 2015

133. E. Kritchanchai and J. S. Yuan, “CMOS voltage-controlled oscillator resilient design for wireless communication applications,” 19th World Multiconference on Systemics, Cybernetics, and Informatics, Orlando, Florida, July 12-15, 2015

134. Y. C. Liu, J. S. Yuan, and E. Kritchanchai, “An implantable cardiovascular pressure monitoring system with on-chip antenna and RF energy harvesting,” 19th World Multiconference on Systemics, Cybernetics, and Informatics, Orlando, Florida, July 12-15, 2015

135. Y. Bi, H. Shamsi, J. S. Yuan, and Y. Jin, “More than Moore in security: Emerging device based low-power differential power analysis countermeasures,” GOMACTech-16, Orlando, Florida, March 12-17, 2016

136. Y. Bi, K. Shamsi, J. S. Yuan, F.-X. Standaert, and Y. Jin, “Leverage emerging technologies for DPA-resilient block cipher design,” Design, Automation and Test in Europe, Dresden, Germany, March 12-18, 2016

137. J. S. Yuan and E. Kritchanchai, “RF energy harvesting using emerging TFET technology,” 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, October 26-28, 2016

138. J. Lin and J. S. Yuan, “A 300 mV, 6-bit ultra-low power SAR ADC,” 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, October 26-28, 2016

139. Q. Alasad, J. S. Yuan, and D. Fan, "Leveraging all-spin logic to improve hardware security," ACM Great Lake Symposium on VLSI, May 10-12, 2017

140. S. Taheri and J. S. Yuan, “Security analysis of computing systems from circuit-architectural perspective,” IEEE Conference on Dependable and Secure Computing, August 7-10, 2017

141. J. Lin and J. S. Yuan, “Capacitor-less RRAM-based stochastic neuron for event-based unsupervised learning,” IEEE Biomedical Circuits and Systems Conference, October 19-21, 2017

142. A. Binder and J. S. Yuan, “Optimization of an enhancement-mode AlGaN/GaN/AlGaN DHFET towards a high breakdown voltage and low figure of merit,” IEEE Workshop on Wide Bandgap Power Devices and Applications, October 30 - November 1, 2017

143. Q. Alasad and J. S. Yuan, “Logic obfuscation against IC reverse engineering attacks using polymorphic gates,” IEEE International Conference on Computer Design, November 5-8, 2017

144. A. Oberai and J. S. Yuan, “Fault localization by finding schematic of devices connecting all emission sites in photon emission microscope image,” 43rd International Symposium for Testing and Failure Analysis, November 5-9, 2017

145. B. Krishnan, A. Kuma, A. Velaga, A. Binder, J. S. Yuan, J. Su, and A. Paranjpe, “TEM microstructural analysis of 8” AlxGa1-xN based enhancement mode HEMTs and correlation of device reliability issues with lattice defects,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 12-15, 2018

146. Q. Alasad, J. S. Yuan, and J. Lin, “Resilient AES against side-channel attack using all-spin logic,” ACM Great Lake Symposium on VLSI, May 23-25, 2018

147. W. Yang, J. S. Yuan, B. Krishnan, A. J. Tzou, and W. K. Yeh, “C-V measurement under different frequencies and pulse-mode voltage stress to reveal shallow and deep trap Effects of GaN HEMTs", IEEE 6th Workshop on Wide Bandgap Power Devices & Applications, October 31 - November 2, 2018

148. M. Salem, S. Taheri, and J. S. Yuan, “ECG arrhythmia classification using transfer learning from 2-dimensional deep CNN features,” IEEE Biomedical Circuits and Systems Conference, October 17-19, 2018

149. M. Salem, S. Taheri, and J. S. Yuan, “Anomaly generation using generative adversarial networks in host based intrusion detection,” 9th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, November 8-10, 2018

150. B. Krishnan, A. Velaga, A. Binder, and J. S. Yuan, “Analysis of defect induced performance degradation in GaN HEMTs”, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 25-28, 2019

151. A. Keshavarzi, M. Salem, J. S. Yuan, and D. Chakrabarti, “Use of artificial intelligence for accelerated malaria drug discovery,” Florida Malaria Research Consortium, March 8-9, 2019

152. W. Yang, J. S. Yuan, B. Krishnan, and P. Shea, “Low-side GaN power device dynamic Ron characteristics under different substrate biases,” International Reliability Physics Symposium, March 31 - April 4, 2019

153. W. Yang and J. S. Yuan, “Experimental verification of substrate bias effect on gate charge for GaN HEMTs,” Compound Semiconductor Week, May 19-23, 2019

154. Z. He, J. Lin, R. Ewetz, J. S. Yuan, and D. Fang, “Noise injection adaption: End-to-end ReRAM crossbar non-ideal effect adaption for neural network mapping,” Design Automation Conference, June 3-5, 2019

155. W. Yang, N. Stoll, J. S. Yuan, and B. Krishnan, “ESD behavior of GaN-on-Si power devices under TLP/VFTLP measurements,” IEEE Workshop on Wide Bandgap Power Devices and Applications, October 28-31, 2019

156. W. Yang, J. S. Yuan, B. Krishnan, and P. Shea, “Experimental evaluation of time-dependent dielectric breakdown for GaN MIS HEMTs under various substrate biases,” IEEE Workshop on Wide Bandgap Power Devices and Applications, October 28-31, 2019

157. M. Safayatullah, W. Yang, J. S. Yuan, and B. Krishnan, “Switching loss characterization of GaN-based buck converter under different substrate biases,” IEEE Workshop on Wide Bandgap Power Devices and Applications, October 28-31, 2019

158. J. Lin, M. Salem, J. S. Yuan, L. Liebmann, J. Fulford, and A. Devillers, “Artificial intelligence enhanced place-and-route of 3D process-in-memory accelerators,” 26th Lithography Workshop, November 3-7, 2019

159. A. K. Arshadi, M. Salem, and J. S. Yuan, “Artificial intelligence of non-target drug discovery for biomedical applications,” Precision Medicine World Conference, January 21-24, 2019

160. B. Krishnan, A. Velaga, J. Callahan, A. Binder, and J. S. Yuan, “Performance and reliability improvement of AlxGa1-xN high electron mobility transistors by a novel superlattice structure aided strain management”, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 16-19, 2020

161. W. Yang, J. S. Yuan, B. Krishnan, A. J. Tzou, and W. K. Yeh, “Substrate bias effect on dynamic characteristics of monolithically integrated GaN half-bridge,” International Reliability Physics Symposium, March 29 - April 2, 2020

162. W. Yang, J. S. Yuan, and B. Krishnan, “ESD robustness of GaN-on-Si power devices under substrate biases by means of TLP/VFTLP tests,” International Reliability Physics Symposium, March 29 - April 2, 2020

163. A. Mahdavian, M. Salem, A. Shojaei, J. S. Yuan, and A. Oloufa, “Forecasting highway construction cost items using machine learning algorithms,” International Conference on Transportation and Development, May 26-29, 2020