I've been told that Make is not the right tool for scripting a digital flow. Well, TCL isn't the right scripting language for synthesis tools, and we're stuck with that too, right? So, in the spirit of antiquated, difficult-to-use EE tools, here we go!
Goal: type "make" -> voila! you have a drc-lvs clean layout, schematic, and behavioral netlist in Cadence. Obviously the user must setup where the pins go, timing constraints, floorplanning, and the like beforehand.