Verilog in one page:
http://iroi.seu.edu.cn/books/asics/Book/CH11/CH11.14.htm#pgfId=7368
Parameterized Modules:
http://www.asic-world.com/verilog/para_modules1.html
Include files:
http://v2kparse.sourceforge.net/includes.pdf
Preventing Errors:
Wire instances by name, not order
Use `default_nettype none to prevent a bus that wasn't declared from defaulting to a 1 bit wire.
Xilinx ram inference override in verilog: (* ram_style = "block/distributed/etc" *) reg ...
Transcendental Math for Testbenches
(sin, cos, exp, log)
http://www.cse.lehigh.edu/~caar/marnold/papers/sanjose_hdlcon.doc
http://www.cs.uwyo.edu/~marnold/verilogmath.html -- this link is down and I can't find the header file posted online anywhere!
Reading and Writing to/from Files:
http://larc.ee.nthu.edu.tw/~lmdenq/doc/fileio.htm
A neat way to make a binary to thermometer decoder:
// Dan Yeager, 2012 module bin2therm (binin, thermout );parameter NBIN = 2;parameter NTHERM = (1<<NBIN)-1;input [NBIN-1:0] binin;output [NTHERM-1:0] thermout; generate genvar i;for(i=0; i<=NTHERM-1; i=i+1) begin : foo assign thermout[i] = (binin > i) ? 1 : 0;end // for endgenerate endmodule
Note: this decodes binary 0 to all thermometer 0's. Its easy to modify it so that binary 0 decodes to thermometer 0000...00001.
the "begin : foo" is to name the generate block. Why this is necessary, I have no idea. Foo should be a unique identifier for each generate statement.
Instantiate like this:
// Dan Yeager, 2012parameter NBIN = 8;parameter NTHERM = (1<<NBIN)-1;wire [NBIN-1:0] binin;wire [NTHERM-1:0] thermout; bin2therm #(.NBIN(NBIN)) dut ( binin, thermout );
General Notes:
http://www.asic-world.com/verilog/verilog2k2.html
How to make a mux:
http://electrosofts.com/verilog/mux.html
Multipliers:
Examples of multiplier implementations in verilog:
http://www.ece.lsu.edu/ee3755/2002/l07.html
Notes on correct and incorrect multiplication of signed and unsigned numbers:
http://www.uccs.edu/~gtumbush/...papers/Tumbush%20DVCon%2005.pdf