VLSI-SDA Lab 구성원들이 함께 체육활동을 즐기고 소통하며 친목을 다지는 뜻깊은 시간을 보냈습니다.

We had a great time enjoying sports activities together with all the VLSI-SDA Lab members. 

VLSI-SDA Lab 연구팀이 63번째 Design Automation Conference에 참가했습니다.

• Poster Presentations

1. Ijun Jang et al., "Hierarchical Learning–Based Digital Circuit Design Tuning Framework for Power-Delay Optimization"

2. Jaeseung Baik, et al., "Split–and–Sync Bayesian Learning–Driven SRAM Compiler: Automatic Design Tuning with Optimal Banking"

VLSI-SDA Lab 연구팀이 2026년 대한전자공학회 하계종합학술대회에 참가했습니다.

• Poster Presentations

1. Donghyeon Ko,  Seungwon Son et al., "Hierarchical Optimization-Based Design Space Exploration for Adder Tree"

2. Taemin Kim, Taewoo Kim, et al., "Ultra-Fast Power Estimation Framework For Adder Tree using Unit-Cell based on LUT Modeling"

3. Donghyeon Ko, et al., " Counter-Based Sequential Accumulation for Area-Efficient Digital SRAM CIM"

4. Aiganym Zhalinova, et al., "SRAM CCS Characterization Acceleration via VDD-Weighted Anchor Selection and Delaunay-Based PVT Interpolation"

졸업한 모든 VLSI-SDA Lab 구성원들과 함께 즐거운 시간을 보냈습니다.

We had a great time with all the VLSI-SDA Lab members who graduated.

VLSI-SDA Lab 연구팀이 2026년 한국반도체산업협회 제 33회 한국 반도체학술대회에 참가했습니다.

• Poster Presentations

1. Dahun Ko, et al., "Learning Based Co-Optimization of Architecture and Transistor-Level Design for Power-Efficient Adder Tree in SRAM-Based In-Memory Computing"

2. Sejun Park, et al., "Energy-Efficient SRAM In-Memory Computing Circuit Enabled by Machine Learning-Based Design Optimization"