Publications

[2024]

D. Kim, S. Kim, J. Lee, H. Kim, S. Lee, J. Park and H. Jeong, “Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation,” 2024 ACM/IEEE Design Automation Conference (DAC 2024), accepted as WIP poster.

W. Jo, G. Kim, S. Park, S-O. Jung and H. Jeong, "An instant leafcell layout auto-generator for area compact memory design automation, "2024 ACM/IEEE Design Automation Conference (DAC 2024), accepted as WIP poster.

S. Park, J. Moon, G. Kim, D. Kim, S-O. Jung, B. Ham and H. Jeong, “""Efficient Prediction of SRAM Read Access Time and Yield via Neural Network Leveraging Transfer Learning and Transformer Models," 2024 ACM/IEEE Design Automation Conference (DAC 2024) , accepted as WIP poster.

[2023]

Sangheon Lee, Kwanwoo Park, and Hanwool Jeong, “Design of High-speed Low Power Sensing Circuit for Nano-scale Embedded Memory,” for Sensors, Dec. 2023.

Inseong Jeon, Hyeonho Park Taehwan Yoon and Hanwool Jeong “High Efficiency Variation-Aware SRAM Timing Characterization via Machine Learning-Assisted Netlist Extraction”, IEEE Transactions on Circuits and Systems-2, Sept. 2023

Junseo Lee, Jihwan Park, Seokhun Kim and Hanwool Jeong “Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization”, IEEE Transactions on Circuits and Systems-1, Sept. 2023

Junseo Lee, Jihwan Park, Inseong Jeon and Hanwool Jeong, "Machine Learning Based Design Methodology for Power Optimization of Wide Range SRAM," 60th Design Automation Conference - (DAC) 2023.

Inseong Jeon, Hyunho Park, Junseo Lee, Taehwan Yoon and Hanwool Jeong, "Machine-learning based Netlist Reduction for Efficient Variation-Aware Timing Characterization in SRAM," 60th Design Automation Conference - (DAC) 2023.

Sangheon Lee, Jaehyun Park, Hanwool Jeong "Cross-Coupled nFET Preamplifier for Low Voltage SRAM," IEEE Transactions on Circuits and Systems-2, Mar. 2023

Jihwan Park, Hanwool Jeong, "Energy-Efficient Wide-Range Level Shifter with a Logic Error Detection Circuit," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2023

T. Yoon, H. Jeong, "Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 8, pp. 2618-2630, Aug. 2023,

Jaehyun Park, Sangheon Lee, Hanwool Jeong, "Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM" IEEE Transactions on Circuits and Systems-1, vol. 70, no. 2, pp. 797-805, Feb. 2023

[2022]

T. Yoon, J. Park, H. Jeong, "Design of Static Random-Access Memory Cell for Fault Tolerant Digital System." Applied Sciences, 12(22), 11500.

H. Park, H. Jeong, "Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead," IEEE Transactions on Very Large Scale Integration (VLSI) Systems

H. Jeong, Y.H. Yang, J.H. Lee, J.S. Kim and S.O. Jung, “Static Read Stability and Write Ability Metrics in FinFET based SRAM Considering Read and Write Assist Circuits,” International Conference on Electronics, Circuits, and Systems, 2012

J. Lee, H. Jeong, Y.H. Yang, J.S. Kim and S.O. Jung, “Impact of fin thickness and height on Read Stability / Write Ability in Tri-Gate FinFET based SRAM,” International SoC Design conference, 2012

H. Jeong, Y.H. Yang, J.H. Lee, J.S. Kim and S.O. Jung, “SRAM Read Stability and Write Ability Metrics in the Aspect of Accurate Yield Estimation with Supply Voltage Scaling in 22nm FinFET Based SRAM,” International Conference on Electronics, Information and Communication, 2012

[2021]

G. Baek, H. Jeong, “High-Density SRAM Read Access Yield Estimation Methodology " IEEE Access, 2021

H. Jeong, T. Kim, CN Park, H. Kim, T. Song, and S.-O. Jung , “A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation,"in IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 554-565, Feb. 2021.

[~2020]

T. Kim, H. Jeong, JH Park, H. Kim, T. Song, and S.-O. Jung , "An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache " IEEE Access

H. Jeong, J. Park, S.C. Song, and S.-O. Jung, “Self-Timed Pulsed Latch for Low Voltage Operation with 77% Hold Time Reduction," IEEE Journal of Solid-State Circuits, Vol. 54, No. 8, Pages 2304-2315

H. Jeong, S. Oh, T. W. Oh, H. Kim, C. N. Park, W. Rim, T. Song, and S.-O. Jung, “Bitline Charge-Recycling SRAM Write Assist Circuitry for Improvement and Energy Saving," IEEE Journal of Solid-State Circuits, Vol. 54, Issue. 3, Pages 896-906

H. Jeong, T. W. Oh, S. C. Song, and S.-O. Jung, "Sense Amplifier-Based Flip Flop with Transition Completion Detection for Low Voltage Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 4, Pages 609-620

T. W. Oh, H. Jeong, J. Park, and S.-O. Jung , "Pre-charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 10, Pages 2737-2747

T. H. Choi, H. Jeong, Y. Yang, J. Park, and S.-O. Jung , "SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 8, Pages 2063-2072

T. W. Oh, H. Jeong, K. Kang, J. Park, Y. Yang, and S.-O. Jung, "Power-Gated 9T SRAM Cell for Low-Energy Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 3, Pages 1183-1187

H. Jeong, J. Park, T. W. Oh, W. Rim, T. Song, G. Kim, H-S. Won, and S.-O. Jung, "Bit-line Precharging and Preamplifying Switching PMOS for High-Speed Low-Power SRAM," IEEE Transactions on Circuits and Systems II, Vol. 63, No. 11, Pages 1059-1063

K. Kim, H. Jeong, J. Park, and S.-O. Jung, "Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution," IEEE Transactions on Circuits and Systems II, Vol. 63, No. 10, Pages 964-968

Y. Yang, H. Jeong, S. C. Song, J. Wang, G. Yeap, S.-O. Jung, "Single Bit-line 7T SRAM Cell for Near-threshold Voltage Operation with Enhanced Performance and Energy in 14 nm FinFET Technology," IEEE Transactions on Circuits and Systems I, Vol. 63, No. 7, Pages 1023-1032

K. Kang, H. Jeong, Y. Yang, J. Park, K, Kim, and S.-O. Jung, "Full-Swing Local Bit-Line SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 4, Pages 1342-1350

G. Kaushal, H. Jeong, S. Maheshwaram, S. K. Manhas, S. Dasgupta, and S.-O. Jung, "Low power SRAM design for 14nm GAA Si-nanowire technology," Microelectronics Journal, Vol. 46, No. 12, Pages 1239-1247

H. Jeong, T. Kim, T. Song, G. Kim and S.-O. Jung, "Trip-point Bit-line Precharge Sensing Scheme for Singleended SRAM" IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 7, Pages 1370-1374

J. Park, H. Jeong, Y. Yang, S. C. Song, J. Wang, G. Yeap, and S.-O. Jung, "Design of a 22-nm FinFET-based SRAM with Read Buffer for Near-Threshold Voltage Operation" IEEE Transactions on Electron Devices, Vol. 62, No. 6, Pages 1698-1704

H. Jeong, K. Kang, T. Song, G .Kim, H.-S. Won, and S.-O. Jung, " Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 6, Pages 1555-1563

H. Jeong, Y. Yang, S. C. Song, J. Wang, G. Yeap, and S.-O. Jung, "Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region" IEEE Transactions on Electron Devices, Vol. 62, No. 6, Pages 1754-1759

H. Jeong, T. Kim, Y. Yang, T. Song, G .Kim, H.-S. Won, and S.-O. Jung, "Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 4, Pages 1062-1070

H. Jeong, Y. Yang, J.Lee, J. Kim, and S.O. Jung “One-sided Static Noise Margin and Gaussian-tail-fitting Method for SRAM," IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 6, Pages 1262-1269

T. Na, H. Jeong, S. H. Woo, J. Kim, S.-O. Jung “Comparative Study of Various Latch-Type Sense Amplifiers," IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 2, Pages 425-429

I. Lee, H. Jeong, S. Baeck, S. Gupta, C. Park, D. Seo, J. Choi, J. Kim, H. Kim, J. Kang, S. Jang, D. Moon, S. Han, T. Kim, J. Lim, Y. Park, H. Hwang, J. Kang, J. Choi, T. Song, "A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology", 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

J. Park, H. Jeong, and S.-O. Jung, “Pulsed PMOS Sense Amplifier for High Speed Single-Ended SRAM,” International Conference on Electronics, Information, and Communication (ICEIC) 2018.

T. H. Choi, H. Jeong, and S.-O. Jung, “Fast Monte-Carlo Analysis Method of Ring Oscillators with Neural Networks,” International Conference on Electronics, Information, and Communication (ICEIC) 2018.

J. Park, H. Jeong, H. J. Kim, and and S.-O. Jung, “Low Power SRAM Bitcell Design for Near-Threshold Operation,” IEEE/IEIE International Conference on Consumer Electronics Asia (ICCE-Asia), 2016.

S. Oh, H. Jeong and S. -O. Jung, "Comparative Analysis on Replica Techniques for Bit-Line Tracking in 14-nm node," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2016

T. Kim, H. Jeong and S. -O. Jung, "Evaluation of Threshold Voltage Extraction Methods in Deep-submicron Technology," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2016

J. Park, H. Jeong and S.-O. Jung, “10T SRAM with Bit-Interleaving Structure for Near-Threshold Operation,” International Conference on Electronics, Information, and Communication (ICEIC) 2016.

T. Na, H. Jeong, J. P. Kim, S.H. Kang, and S.O. Jung, “Efficiency Analysis of Importance Sampling in Deep Submicron STT-Ram Design Using Uncontrollable Industry-Compatible Model Parameter,” IEEE International Conference on Electronics, Circuits, & Systems (ICECS), 2015.

H. Jeong, T. Kim, T.S, G.K, and S.O. Jung, “Pseudo NMOS Based Sense Amplifier for High Speed Single-Ended SRAM,” International Conference on Electronics Circuits and Systems, 2014.

G. Kaushal , R. Vaddi, S. K, S. N. Rao, V. K, R. Ramya, S. Shaik, H. Jeong, and S. O. Jung, “Design and Performance Benchmarking of Steep-Slope Tunnel Transistors for Low Voltage Digital and Analog Circuits Enabling Self-Powered SOCs,” International SoC Design Conference, 2014.

B. Song, T. Na, H. Jeong, S. H. Kang, J. P. Kim and S. O. Jung, “Comparative Analysis of Using Planar MOSFET and FinFET as Access Transistor of STT-RAM Cell in 22-nm Technology Node,” International SoC Design Conference, 2014.

H. Jeong, T. Kim, T. Song, G. Kim, and S.O. Jung, “Half Bit-line Voltage Sensing Amplifier For High Speed Single-Ended SRAM Sensing,” International Conference on Electronics, Information and Communication, 2014.

K. Kang, H. Jeong, J. Lee, and S.O. Jung, “Comparative Analysis of 1:1:2 and 1:2:2 FinFET SRAM Bit-Cell Using Assist Circuit,” International SoC Design Conference, 2013.

D.H. Jung, H. Jeong, T. Song, G. Kim and S.O. Jung, “Source Follower Based Single Ended Sense Amplifier for Large Capacity SRAM Circuit,” International SoC Design Conference, 2013.

J. Lee, H. Jeong, K. Kang, Y. Yang, J. Kim, and S.O. Jung, "Read and Write Yield Improvement of FinFET Based SRAM Using Non-Minimal Gate Length," International Technical Conference on Circuits/Systems, Computers and Communications, 2013