Citations published by [Google Scholar]

ORCiD 0000-0002-6216-214X

Refereed Journal Papers

• 1. Y.C. Lu, J.-K. Huang, K.-Y. Chao, L.-L. Li, and V. P.-H. Hu, “Performance Projection of Si- and 2D Material based SRAM Circuit Ranging From 16 nm to 1 nm Nodes,” Nature Nanotechnology, 2024. https://doi.org/10.1038/s41565-024-01693-3 

  2. C.-H. Wu, J. Liu, X.-T. Zheng, H.-F. Chuang, Y.-M. Tseng, M. Kobayashi, C.-J. Su, and V. P.-H. Hu, "Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing with Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design," IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 3371-3376, May 2024, doi: 10.1109/TED.2024.3377191.

  3. M. Gupta and V. P.-H. Hu, "Improved Scalability of Negative Capacitance Junctionless Transistors With Underlap Design," IEEE Transactions on Electron Devices, vol. 70, no. 8, pp. 4043-4048, Aug. 2023, doi: 10.1109/TED.2023.3285511.

  4. C.-J. Liu, Y. Wan, L.-J. Li, C.-P. Lin, T.-H. Hou, Z.-Y. Huang, and V. P.-H. Hu, "2D Materials-Based Static Random-Access Memory," Advanced Materials, 2022, vol. 34, 2107894, https://doi.org/10.1002/adma.202107894.

  5. F. Mo, J. Xiang, X. Mei, Y. Sawabe, T. Saraya, T. Hiramoto, C.-J. Su, V. P.-H. Hu, and M. Kobayashi, "Efficient Erase Operation by GIDL Current for 3D structure FeFET with Gate Stack Engineering and Compact Long-term Retention Model," IEEE Journal of the Electron Devices Society, vol. 10, pp. 115-122, 2022, doi: 10.1109/JEDS.2022.3142046. (Leo Esaki Award)

  6. M. Gupta and V. P.-H. Hu, "Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications," IEEE Transactions on Electron Devices, vol. 68, no. 8, pp. 4136-4143, Aug. 2021, doi: 10.1109/TED.2021.3089105.

  7. M. Gupta and V. P.-H. Hu, "Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors," ECS J. Solid State Sci. Technol. 10 065009, 2021. DOI: https://doi.org/10.1149/2162-8777/ac0607

  8. V. P.-H. Hu, C.-W. Su, Y.-W. Lee, T.-Y. Ho, C.-C. Cheng, T.-C. Chen, T. Y.-T. Hung, J.-F. Li, Y.-G. Chen, and L.-J. Li, "Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2 FETs for SoC Scaling," IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4216-4221, Oct. 2020. DOI: 10.1109/TED.2020.3018099. 

  9. V. P.-H. Hu, H.-H. Lin, Y.-K. Lin, and C. Hu, "Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)," IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2593-2599, June 2020. DOI: 10.1109/TED.2020.2986793

  10. M. Gupta and V. P.-H. Hu, "Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications," IEEE Electron Device Letters, vol. 41, no. 3, pp. 473-476, March 2020. DOI: 10.1109/LED.2020.2969210

  11. V. P.-H. Hu, P.-C. Chiu, and Y.-C. Lu, "Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs," IEEE Journal of the Electron Devices Society, vol. 7, pp. 295-302, 2019. DOI: 10.1109/JEDS.2019.2897286

  12. V. P.-H. Hu and P.-C. Chiu, "Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs," 2018 Jpn. J. Appl. Phys. 57 04FD02. https://doi.org/10.7567/JJAP.57.04FD02

  13. V. P.-H. Hu and C.-T. Wang, "Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression," 2018 Jpn. J. Appl. Phys. 57 04FD18. DOI: https://doi.org/10.7567/JJAP.57.04FD18

  14. V. P.-H. Hu, "Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier," IEEE Journal of the Electron Devices Society, vol. 5, no. 2, pp. 107-111, March 2017. DOI: 10.1109/JEDS.2016.2644724

  15. C.-H. Yu, M.-L. Fan, K.-C. Yu, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Evaluation of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Devices for SRAM Applications," IEEE Transactions on Electron Devices, vol. 63, no. 2, pp. 625-630, February 2016. DOI: 10.1109/TED.2015.2505064

  16. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, " Analysis of GeOI FinFET 6T SRAM Cells with Variation-Tolerant WLUD Read-Assist and TVC Write-Assist," IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 1710-1715, June 2015. DOI: 10.1109/TED.2015.2412973

  17. C.-W. Hsu, M.-L. Fan, V. P.-H. Hu, and Pin Su, "Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET," IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 194-199, May 2015. DOI: 10.1109/JEDS.2015.2408356

  18. Y.-N. Chen, C.-J. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits," Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 101-115, May 2015. https://doi.org/10.3390/jlpea5020101

  19. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, C.-W. Hsu, Pin Su and C.-T. Chuang, "Investigation of Back gate-Biasing Effect for Ultra-Thin-Body III-V Heterojunction Tunnel FET," IEEE Transactions on Electron Devices, vol. 62, no. 1, pp. 107-113, January 2015. DOI: 10.1109/TED.2014.2368581

  20. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFETand Mixed TFET-MOSFET SRAM Cell with Write-Assist Circuits," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 4, pp. 389-399, December 2014. DOI: 10.1109/JETCAS.2014.2361072

  21. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Evaluation of Sub-0.2V High-Speed Low-Power Circuits using Hetero-Channel MOSFET and Tunneling FET Devices," IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 61, no. 12, 3339-3347, December 2014. DOI: 10.1109/TCSI.2014.2335032

  22. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Stability and Performance Optimization of Hetero-Channel Monolithic 3D SRAM Cells Considering Interlayer Coupling," IEEE Transactions on Electron Devices, vol. 61, no. 10, pp. 3448-3455, October 2014. DOI: 10.1109/TED.2014.2348856

  23. M.-L. Fan, S.-Y. Yang, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, "Single-Trap-Induced Random Telegraph Noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and Logic Circuits," Microelectronics Reliability (Invited), vol. 54, issue 4, pp. 698–711, April 2014. https://doi.org/10.1016/j.microrel.2013.12.026

  24. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET," IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3596-3600, October 2013. DOI: 10.1109/TED.2013.2278032

  25. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Threshold Voltage Design of UTB SOI SRAM with Improved Stability/Variability for Ultra-Low Voltage near Subthreshold Operation," IEEE Transactions on Nanotechnology, vol. 12, no. 4, pp. 524-531, July 2013. DOI: 10.1109/TNANO.2011.2105278

  26. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Analysis of Single-Trap-Induced Random Telegraph Noise and Its Interaction with Work Function Variation for Tunnel FET," IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 2038-2044, June 2013. DOI: 10.1109/TED.2013.2258157

  27. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Design and Analysis of Robust Tunneling FET SRAM," IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 1092-1098, March 2013. DOI: 10.1109/TED.2013.2239297

  28. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Threshold Voltage Design and Performance Assessment of Hetero-channel SRAM Cells," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 147-152, January 2013. DOI: 10.1109/TED.2012.2228863

  29. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications," IEEE Transactions on Circuits and Systems - II: Express Briefs, vol. 59, no. 12, pp. 878-882, December 2012. DOI: 10.1109/TCSII.2012.2231016

  30. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Analysis of Single Trap Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell and Logic Circuits," IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2227-2234, August 2012. DOI: 10.1109/TED.2012.2200686

  31. C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, "Impact of Quantum Confinement on Back gate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETs," IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1851-1855, July 2012. DOI: 10.1109/TED.2012.2194499

  32. C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, "Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs," IEEE Transactions on Nanotechnology, vol. 11, no. 2, pp. 287-291, March 2012. DOI: 10.1109/TNANO.2011.2169084

  33. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Band-to-Band Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs using Transistor Stacking," IEEE Electron Device Letters, vol. 33, no. 2, pp. 197-199, February 2012. DOI: 10.1109/LED.2011.2177955

  34. C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems,vol. 20, no. 7, pp. 1201-1210, July 2012. DOI: 10.1109/TVLSI.2011.2156435

  35. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation and Temperature Sensitivity,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 335-342, September 2011. DOI: 10.1109/JETCAS.2011.2163691

  36. V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, P. Su, and C.-T. Chuang, “FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics,” IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 805-811, March 2011. DOI: 10.1109/TED.2010.2099661

  37. V. P.-H. Hu, Y.-S. Wu, and P. Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body Germanium-On-Nothing (GeON) MOSFET," IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 325-330, March 2011. DOI: 10.1109/TNANO.2010.2041010

  38. M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, C.-Y. Hsieh, P. Su, and C.-T. Chuang, “Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability – A Model-Based Approach,” IEEE Transactions on Electron Devices,vol. 58, no. 3, pp. 609-616, March 2011. DOI: 10.1109/TED.2010.2096225

  39. Y.-S. Wu, H.-Y. Hsieh, V. P.-H. Hu, and P. Su, "Impact of Quantum Confinement on Short-Channel Effects for Ultra-Thin-Body Germanium-On-Insulator MOSFETs," IEEE Electron Device Letters, vol. 32, no. 1, pp. 18-20, January 2011. DOI: 10.1109/LED.2010.2089425

  40. M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Investigation of Cell Stability and Write-ability of FinFET Subthreshold SRAM using Analytical SNM Model," IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1375-1381, June 2010. DOI: 10.1109/TED.2010.2046988

  41. V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, P. Su, and C.-T. Chuang, "Static Noise Margin of Ultra-Thin-Body SOI Subthreshold SRAM Cells - An Assessment Based on Analytical Solution of Poisson's Equation," IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 2120-2127, September 2009. DOI: 10.1109/TED.2009.2026322

  42. V. P.-H. Hu, Y.-S. Wu and P. Su, "Investigation of electrostatic integrity for ultra-thin-body GeOI MOSFET using analytical solution of Poisson's equation," Semiconductor Science and Technology, vol. 24, no. 4, April 2009. https://doi.org/10.1088/0268-1242/24/4/045017

Conference Papers: 

• 1. C.-H. Wu, J. Liu, X.-T. Zheng, Y.-M. Tseng, M. Kobayashi, V. P.-H. Hu*, and C.-J. Su*, “Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design,” 2023 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, December 2023.

  2. M. Lee, Z.-Y. Huang, S.-F. Fang, Y.-C. Lu, and V. P.-H. Hu, “Energy- and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors,” 2022 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, December 2022. 

  3. V. P.-H. Hu, C.-J. Liu, H.-L. Chiang, J.-F. Wang, C.-C. Cheng, T.-C. Chen, and M.-F. Chang, “High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing,” 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, December 2021.DOI: 10.1109/IEDM19574.2021.9720511 

  4. M. Gupta and V. P.-H. Hu, “Optimization of Junctionless Ferroelectric Field-Effect Transistors for Non-Volatile Memory Applications,” International Conference on Solid State Devices and Materials (SSDM), Japan, September 2021.

  5. V. P.-H. Hu and C.-J. Liu, "Static Noise Margin Analysis for Cryo-CMOS SRAM Cell," 2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT2021), Taiwan, August 2021. 

  6. F. Mo, J. Xiang, X. Mei, Y. Sawabe, T. Saraya, T. Hiramoto, C.-J. Su, V. P.-H. Hu, and M. Kobayashi, "Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-term FeFET Retention Model," 2021 Symposia on VLSI Technology & Circuits (VLSI), Kyoto, Japan, June 2021.

  7. V. P.-H. Hu, Cheng-Wei Su, Chun-Chi Yu, Chang-Ju Liu, and Cheng-Yang Weng, “Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node,” Proceedings of 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, May 2021. 

  8. M. Gupta and V. P.-H. Hu, “Improved Switching Time in Negative Capacitance Junctionless Transistors," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2021.

  9. C. J. Su, M. K. Huang, K. S. Lee, V. P.-H. Hu et al., "3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T 1R Configuration Demonstrated on Full Wafer," 2020 International Electron Devices Meeting (IEDM), San Francisco, USA, December 2020.

  10. Y.-W. Lee and V. P.-H. Hu, “Improved Energy Efficiency for Ferroelectric FET Non-volatile Memory using Split-gate Design," Proceedings of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, May 2020.

  11. M. Gupta and V. P.-H. Hu, “Subthreshold Behavior of Ferroelectric Junctionless Transistor," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2020.

  12. M. Gupta and V. P.-H. Hu, “Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications,” 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), San Jose, California, USA, October 2019.

  13. T.-Y. Ho and V. P.-H. Hu, “Design Space Exploration of 1T Non-Volatile Ferroelectric FET Memory for Logic-In-Memory Applications,” Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, September 2019.

  14. V. P.-H. Hu, H.-H. Lin, Z.-A. Zheng, Z.-T. Lin, Y.-C. Lu, T.-Y. Ho, Y.-W. Lee, C.-W. Su, and C.-J. Su, “Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications,” 2019 Symposia on VLSI Technology & Circuits (VLSI), Kyoto, Japan 2019. DOI: 10.23919/VLSIT.2019.8776555

  15. Z.-T. Lin and V. P.-H. Hu, “Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFET by Substrate Doping Optimization,” 2019 Silicon Nanoelectronics Workshop (SNW), Tokyo, Japan, 2019.

  16. Y.-C. Lu and V. P.-H. Hu, “Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations,” 2019 Silicon Nanoelectronics Workshop (SNW), Tokyo, Japan, 2019.

  17. Z.-A. Zheng and V. P.-H. Hu, “Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation,” Proceedings of 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019. DOI: 10.1109/ISCAS.2019.8702126

  18. H.-H. Lin and V. P.-H. Hu, “Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET”, International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, March 2019. DOI: 10.1109/ISQED.2019.8697625

  19. Z.-A. Zheng, P.-C. Chiu, and V. P.-H. Hu, “Stability Analysis of Subthreshold/Superthreshold Negative Capacitance FinFET SRAM Cell,” Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2018.

  20. Z.-T. Lin, P.-C. Chiu, and V. P.-H. Hu, “Performance Analysis of Gate-All-Around Negative Capacitance Stacked Nanowire and Negative Capacitance Nanosheet FETs,” Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2018.

  21. V. P.-H. Hu, Y.-C. Lu and P.-C. Chiu, “Investigation of Analog Performance for Negative Capacitance SOI MOSFET considering Line-Edge Roughness,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, US, June 2018.

  22. C.-T. Wang and V. P.-H. Hu, "Analysis of Heterojunction GaAs1-xSbx/In1-yGayAs Tunnel FETs considering Line Tunneling," IEEE International Symposium on Next-Generation Electronics (ISNE), Taipei, Taiwan, May 2018. DOI: 10.1109/ISNE.2018.8394741

  23. Hung Han Lin and V. P.-H. Hu, "Device Design of Vertical Nanowire Ⅲ-Ⅴ Heterojunction TFETs for Performance Enhancement," IEEE International Symposium on Next-Generation Electronics (ISNE), Taipei, Taiwan, May 2018. DOI: 10.1109/ISNE.2018.8394742

  24. P.-C. Chiu and V. P.-H. Hu, "Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation," IEEE Electron Devices Technology and Manufacturing (EDTM), Kobe, Japan, March 2018. DOI: 10.1109/EDTM.2018.8421472

  25. C.-T. Wang and V. P.-H. Hu, "Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling," IEEE Electron Devices Technology and Manufacturing (EDTM), Kobe, Japan, March 2018. DOI: 10.1109/EDTM.2018.8421435

  26. V. P.-H. Hu, P.-C. Chiu, A. B. Sachid, and C. Hu, “Negative Capacitance Enables FinFET and FDSOI Scaling to 2 nm Node,” 2017 International Electron Devices Meeting (IEDM), San Francisco, USA, December 2017. DOI: 10.1109/IEDM.2017.8268443

  27. P.-C. Chiu and V. P.-H. Hu, “Switching Time Analysis of Negative Capacitance UTB GeOI MOSFETs,” Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, September 2017.

  28. C.-T. Wang and V. P.-H. Hu, “III-V Heterojunction TFET with Bandgap Engineering for Performance Enhancement and Ambipolar Leakage Suppression,” Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, September 2017.

  29. P.-C. Chiu and V. P.-H. Hu, "Analysis of Subthreshold Swing and Internal Voltage Amplification for Hysteresis-Free Negative Capacitance FinFETs," IEEE Electron Devices Technology and Manufacturing (EDTM), Toyama, Japan, February 2017. DOI: 10.1109/EDTM.2017.7947539

  30. Zi-Cheng Huang and Vita Pi-Ho Hu, "Switching Time Enhancement for Ultra-Thin-Body InGaAs-OI MOSFET through Underlap Design," 2016 International Electron Devices and Materials Symposium (IEDMS), Taipei, Taiwan, November 2016.

  31. V. P.-H. Hu, “Reliability Analysis for Monolithic 3D UTB GeOI and SOI 6T SRAM Cells considering Interlayer Coupling,” Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September 2016.

  32. V. P.-H. Hu, Pin Su and C.-T. Chuang, "Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-Thin-Body GeOI MOSFETs," Proceedings of 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montréal, Canada, May 2016. DOI: 10.1109/ISCAS.2016.7538995

  33. V. P.-H. Hu, A. B. Sachid, C.-T. Lo, Pin Su and C. Hu, "Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap," 2016 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2016. DOI: 10.1109/VLSI-TSA.2016.7480515

  34. C.-T. Lo, V. P.-H. Hu, and Pin Su, "Higher-k Gate-Dielectric induced Degradation in Electrostatic Integrity and Mitigation by Spacer Design for Multi-Gate InGaAs-OI FinFETs," 2015 International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, November 2015.

  35. K.-C. Yu, C.-H. Yu, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Impacts of Threshold Voltage Design for Monolithic 3D 6T SRAM with Si and InGaAs-n/Ge-p Devices considering Interlayer Coupling," Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, September 2015.

  36. T.-C. Wu, C.-J. Chen, Y.-N. Chen, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications," 28th IEEE International System-On-Chip Conference (SOCC 2015), Beijing, China, September 2015.

  37. (Best Paper Award) V. P.-H. Hu, Pin Su, and C.-T. Chuang, "UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability," 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2015), Hsinchu, Taiwan, June 29 - July 2, 2015. 

  38. T.-C. Wu, C.-J. Chen, Y.-N. Chen, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices," 2015 IEEE International Conference on IC Design and Technology (ICICDT), Leuven, Belgium, June 2015.

  39. V. P.-H. Hu, M.-L. Fan, Pin Su, and C.-T. Chuang, "Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells," Proceedings of 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015.

  40. C.-J. Chen, Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su, and C.-T. Chuang, "Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015.

  41. V. P.-H. Hu, A. B. Sachid, C.-T. Lo, Pin Su and C. Hu, "Electrostatic Integrity and Performance Enhancement for UTB InGaAs-OI MOSFET with High-k Dielectric through Spacer Design," 2015 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2015.

  42. V. P.-H. Hu, M.-L. Fan, Pin Su, and C.-T. Chuang, "Stability Analysis for UTB GeOI 6T SRAM Cells considering NBTI and PBTI," 2015 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2015.

  43. C.-J. Chen, Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Impacts of Work Function Variation and Line-Edge Roughness of TFET and FinFET Devices and Logic Circuits," 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Millbrae, California, October 2014.

  44. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell," IEEE International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA USA, August 2014. 

  45. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Evaluation of Read- and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells," Proceedings of 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014.

  46. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, "Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling," Proceedings of 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014.

  47. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Stability/Performance Assessment of Monolithic 3D 6T/8T SRAM Cells Considering Transistor-Level Interlayer Coupling," Proceedings of 2014 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 2014.

  48. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, "Comprehensive Analysis of Ultra-Thin-Body MOSFETs for Monolithic 3D Logic Circuits with Interlayer Coupling," Proceedings of 2013 International Semiconductor Device Research Symposium (ISDRS), Maryland, USA, December 2013.

  49. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), Monterey, CA, USA, October 2013.

  50. V. P.-H. Hu, H.-H. Shen, M.-L. Fan, P. Su, and C.-T. Chuang, “Leakage-Delay Analysis of InxGa1-xAs-OI FinFETs for Logic Applications,” Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

  51. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, “Investigation of Tunneling FET Device Designs for Improving Circuit Switching Performance and Energy,” Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 2013.

  52. S.-Y. Yang, Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits," Proceedings of the 2013 IEEE International Conference on IC Design and Technology (ICICDT), Pavia, Italy, May 2013.

  53. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices,” Proceedings of the IEEE 2013 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2013.

  54. M.-F. Tsai, M.-L. Fan, C.-H. Pao, Y.-N. Chen, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs," Proceedings of the IEEE 2013 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2013.

  55. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, "Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers," Proceedings of the 2013 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, April 2013.

  56. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates," The International Symposium on Quality Electronic Design (ISQED 2013), Santa Clara, USA, March 2013.

  57. C.-H. Pao, M.-L. Fan, M.-F. Tsai, Y.-N. Chen, V. P.-H. Hu, P. Su, and C.-T. Chuang, "A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits," 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, December 2012.

  58. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, K.-C. Lee, P. Su, and C.-T. Chuang, "Variability Analysis of Sense Amplifier for Subthreshold Ultra-Thin-Body SOI SRAM Applications," Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, Japan, September 2012.

  59. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Stability and Performance Optimization of InGaAs-OI and GeOI Heterochannel SRAM Cells," Proceedings of the 42th European Solid-State Device Research Conference (ESSDERC 2012), Bordeaux, France, September 2012.

  60. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, M.-F. Tsai, C.-H. Pao, P. Su, and C.-T. Chuang, "A Comparative Analysis of Tunneling FET Circuit Switching Characteristics and SRAM Stability and Performance," Proceedings of the 42th European Solid-State Device Research Conference (ESSDERC 2012), Bordeaux, France, September 2012.

  61. C.-H. Pao, M.-L. Fan, M.-F. Tsai, Y.-N. Chen, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Impacts of Random Telegraph Noise on the Analog Properties of FinFET and Trigate Devices and Widlar Current Source," Proceedings of the 2012 IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, USA, May 2012.

  62. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits," Proceedings of the 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, USA, April 2012.

  63. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Comparison of Differential and Large-Signal Sensing Scheme for Subthreshold/Superthreshold FinFET SRAM Considering Variability," Proceedings of the IEEE 2012 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2012.

  64. M.-F. Tsai, B. K.-Y. Lu, M.-L. Fan, C.-H. Pao, Y.-N. Chen, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Impacts of Wire-LER on Nanowire MOSFET Devices, Subthreshold SRAM and Logic Circuits," Proceedings of the IEEE 2012 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2012.

  65. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Comprehensive Analysis of UTB GeOI LogicCircuits and 6T SRAM Cells considering Variability and Temperature Sensitivity," 2011 International Electron Devices Meeting (IEDM), Washington DC, USA, December 2011. DOI: 10.1109/IEDM.2011.6131658

  66. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, "Impact of Single Trap Induced Random Telegraph Noise on FinFET Device and SRAM Stability," Proceedings of the 2011 IEEE International SOI Conference, October 2011.

  67. C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, "Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage Characteristics for Ultra-Thin-Body Germanium-On-Insulator MOSFETs," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, September 2011.

  68. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Analysis of Power-Performance for Ultra-Thin-Body GeOI Logic Circuits,” IEEE International Symposium on Low Power Electronics and Design (ISLPED 2011), Fukuoka, Japan, August 2011. (Best Paper Nomination)

  69. C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs considering Quantum Confinement," Proceedings of the 2011 IEEE International NanoElectronics Conference (INEC), Tao-Yuan, Taiwan, June 2011.

  70. (Outstanding Student Paper Award, 1st PLACE WINNER) V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Variability Analysis of UTB SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation and Temperature Sensitivity,” IEEE International Conference on IC Design and Technology (ICICDT 2011), Taiwan, May 2011. 

  71. Y.-N. Chen, C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, “Impacts of Intrinsic Device Variations on the Stability of FinFET Subthreshold SRAMs,” IEEE International Conference on IC Design and Technology (ICICDT), May 2011.

  72. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Leakage-Delay Analysis of Ultra-Thin-Body GeOI Devices and Logic Circuits,” Proceedings of the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2011.

  73. Y.-S. Wu, H.-Y. Hsieh, V. P.-H. Hu, and P. Su, “Beneficial Effects of Quantum Confinement on Ge and InGaAs Ultra-Thin-Body NMOSFETs,” Proceedings of the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2011.

  74. Y.-N. Chen, C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, “Disturb-Free Independently-Controlled-Gate 7T FinFET SRAM Cell,” Proceedings of the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2011.

  75. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, “Evaluation of Static Noise Margin and Performance of 6T FinFET SRAM Cells with Asymmetric Gate to Source/Drain Underlap Devices,” Proceedings of the 2010 IEEE International SOI Conference, San Diego, California, USA, October 2010.

  76. C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, P. Su, and C.-T. Chuang, “Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs, Proceedings of the 2010 IEEE InternationalSOI Conference, San Diego, California, USA, October 2010.

  77. V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, P. Su, and C.-T. Chuang, "High-k Metal Gate FinFET SRAM Cell Optimization Considering Variability due to NBTI/PBTI and Surface Orientation," Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 2010.

  78. V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, P. Su, and C.-T. Chuang, "FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI and Surface Orientation," Proceedings of the 15th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 269-272, Bologna, Italy, September 2010.

  79. M.-L. Fan, V. P.-H. Hu, C.-Y. Hsieh, P. Su, and C.-T. Chuang, "Subthreshold FinFET SRAM Cell Optimization Considering Surface-Orientation Dependent Variability," Proceedings of the 40th European Solid-State Device Research Conference (ESSDERC), pp. 198-201, September 2010.

  80. M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Investigation of Stability and AC Performance of Sub-threshold FinFET SRAM," Proceedings of the IEEE 2010 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, pp. 66-67, April 2010.

  81. V. P.-H. Hu, Y.-S. Wu, and P. Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeON MOSFET," Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, October 2009.

  82. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Subthreshold SRAM with Enhanced Stability using Ultra-Thin-Body and BOX SOI," Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, October 2009.

  83. M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region," Proceedings of the 2009 IEEE International SOI Conference, Foster City, California, USA, October 2009.

  84. V. P.-H. Hu, M.-L. Fan, P. Su, and C.-T. Chuang, "Impact of Work Function Design on the Stability and Performance of Ultra-Thin-Body SOI Subthreshold SRAM," Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC 2009), Athens, Greece, pp. 145-148, September 2009.

  85. V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, P. Su, and C.-T. Chuang, "Design and Analysis of Ultra-Thin-Body SOI Based Subthreshold SRAM," International Symposium on Low Power Electronics and Design (ISLPED 2009), San Francisco, California, USA, pp. 9-14, August 2009.

  86. V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, P. Su, and C.-T. Chuang, "Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson's Equation," Proceedings of the IEEE 2009 VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, pp. 115-116, April 2009.

  87. V. P.-H. Hu, Y.-S. Wu, and P. Su, "Investigation of Electrostatic Integrity for Ultra-Thin-Body GeOI MOSFET Using Analytical Solution of Poisson’s Equation," Proceedings of the 2008 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2008), Hong Kong, December 2008.