My research interests lie primarily in the design of low power and high performance analog-mixed signal and RF circuits and systems. However I am open to explore new application areas related to integrated circuit design.

Here is the summary of my research work:

Industry Research:

• Xilinx/AMD SerDes Technology Group: High speed wireline transceivers and clocking.

  1. RX DCO and post-scalar design and optimization, clock coupling simulation.

  2. TX frontend driver and output matching network design for 200+Gbps 

• Intel Wireless Communication Research Lab: Clock generators for wireless transceivers and phased-array systems. 

  1. Phased array research presented in ISSCC'19 is highlighted by Intel Newsroom, Electronics Weekly,  EE Times and EE Times India.  Awarded at ISSCC'20 for Outstanding Paper. Appeared at SSCS Magazine article.  

  2. Synthesized MDLL research presented in ISSCC'20 appeared as Session Highlight in the Press Kit. Also appeared at UMN ECE Department website.  Invited and published in JSSC'21.

  3. Efficient reference clock generators  with faster start-up and integrated resonators (MEMS'21, CICC'21, JSSC'22, ISSCC'22). Fast startup technique presented in CICC'21 is invited and published in JSSC'22. Sampling PLL presented in ISSCC'22 appeared in Intel blog and ISSCC Session Highlight in Press Kit.

  4. Calibration techniques for high-speed Data Converters. Presented in ISSCC'24, highlighted by Intel Newsroom.

• Intel Circuit Research Lab: Power delivery network modeling and different voltage droop mitigation schemes

• Rambus: Clock distribution network and topologies in high-speed serial link transceivers 

• Xilinx: Wide tuning range current controlled LC oscillator design for serial-link PLL in 16nm CMOS (MWSCAS'15, 1 US Patent)

• STMicroelectronics: High-speed transmitter, receiver and PLL design for serial-link IPs e.g. HDMI, MPHY etc in advanced CMOS technologies (ISCAS'12, 1 US Patent)

PhD Research:

• Thesis title "Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors"

• Digital low dropout (DLDO) regulator with adaptive sampling clock (ISCAS'17, ISSCC'18, JSSC'19)

• Digital Time based Decision Feedback Equalizer   (VLSIC'17, JSSC'18)

• All digital sub-sampling fractional-N PLL and MDLL design in 65nm CMOS with in-situ jitter and phase-offset detection circuit (VLSIC'15, ISSCC'16, JSSC'17)

• Beat frequency detector based ADC in 65nm CMOS for low swing bio-potential signal detection (CICC'14, CICC'15, BioCAS'18)

• Area efficient and low power frequency-to-current converter based frequency synthesizer in 32nm SOI CMOS with on-chip jitter measurement (TCASII'15)

Masters Research:

• 50GHz quadrature traveling wave oscillator utilizing the area underneath on-chip inductor in 65nm CMOS with on-chip quadrature accuracy measurement circuits (VLSID'13 Best Student Paper Award)