H. C. Chen, et al., "Distributed arithmetic realization of cyclic convolution and its dft application," Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems], pp. 615-629, 2005.
H.-C. Chen, et al., "A memory-efficient realization of cyclic convolution and its application to discrete cosine transform," IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, pp. 445-453, March 2005.
H.-C. Chen, et al., "The long length DHT design with a new hardware efficient distributed arithmetic approach and cyclic preserving partitioning," IEICE Transactions on Electronics, vol. E88, pp. 1061-1069, May 2005.
H.-C. Chen, et al., "A low power and memory efficient distributed arithmetic design and its DCT application," in APCCAS, Tainan, Taiwan, 2004, pp. 805-808.
Filter design
T. S. Chang and C. W. Jen, "Hardware-efficient pipelined programmable FIR filter design," Computers and Digital Techniques, IEE Proceedings-, vol. 148, pp. 227-232, 2001.
T.-S. Chang, et al., "Low-power FIR filter realization with differential coefficients and inputs," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 137-145, Feb. 2000.
T.-S. Chang and C.-W. Jen, "Low power FIR filter realization with differential coefficients and input," in ICASSP, Seattle, WA, USA, 1998, pp. 3009-3011.
Design with subexpression sharing
T.-S. Chang, et al., "Hardware-efficient DFT designs with cyclic convolution and subexpression sharing," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 886-892, Sep. 2000.
T.-S. Chang and C.-W. Jen, "Hardware efficient transform designs with cyclic formulation and subexpression sharing," in ISCAS, Monterey, CA, USA, 1998, pp. 398-401.