W.-C. Tai, et al., "Bandwidth-Rate-Distortion Optimized Motion Estimation," in Proc. IEEE International Conference on Multimedia and Expo, 2009.
Motion compensation
G.-S. Yu and T. S. Chang, "Optimal Data Mapping for Motion Compensation in H.264 Video Decoding," in Signal Processing Systems, 2007 IEEE Workshop on, 2007, pp. 505-508.
T.-S. Chang, et al., "Compact IDCT processor for HDTV applications," in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, Taipei, Taiwan, 1999, pp. 151-158.
C. Chen, et al., "IDCT processor on the adder-based distributed arithmetic," in IEEE Symposium on VLSI Circuits,, Honolulu, HI, USA, 1996, pp. 36-37.
Lossless memory bandwidth compression
L. C. Chiu and T. S. Chang, "A lossless embedded compression codec engine for HD video decoding," in VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on, 2012, pp. 1-4.
Constrained based coding (e.g. power aware/memory bandwidth aware)
W.-C. Chang, et al., " Power-Aware Coding for H.264/AVC Video Encoder," in Proc. VLSI/CAD, 2009.
H.264 Encoder
Whole encoder design published on ISSCC and DAC
Y.-K. Lin, et al., "A 242 mW, 10 mm/sup 2/ 1080 p H.264/AVC high profile encoder chip," presented at the 2008 45th ACM/IEEE Design Automation Conference, 2008.
Y.-K. Lin, et al., "A 242 mW 10 mm/sup 2/ 1080 p H.264/AVC high-profile encoder chip," in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, pp. 314-15, 615.
Intra encoder only design
Y. K. Lin, et al., "A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder," IEEE Transactions on Circuits and Systems for Video Technology, vol. 19, pp. 432-436, Mar 2009.
C.-W. Ku, et al., "A High Definition H.264/AVC Intra Frame Codec IP for Digital Video and Still Camera Applications," IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, pp. 917-928, August 2006.
D.-W. Li , et al., "A 61MHz 72K Gates 1280x720 30fps H.264 intra encoder," in ICASSP, 2007.
C. C. Cheng, et al., "A 1280x720 Pixels 30Frames/s H.264/MPEG-4 AVC Intra Encoder," in ISCAS, 2006, pp. 5335-5338.
Multi-resolution Integer ME + single step Fractional-pel ME
Y.-K. Lin, et al., "A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video," IEEE Transactions on Circuits and Systems I: Regular Papers,, vol. 55, pp. 1526-1535, June 2008.
Y.-J. Wang, et al., "A Fast Algorithm and Its VLSI Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding," IEEE Transactions on Circuits and Systems for Video Technology, pp. 578-583 May 2007.
Y. J. Wang, et al., "A Fast Fractional Pel Motion Estimation Algorithm for H.264/MPEG-4 AVC," in ISCAS, 2006, pp. 3974-3977.
T.-Y. Kuo, et al., "SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm for HDTV Sized H.264 Video Coding," in ICASSP, 2007.
C.-C. Lin, et al., "PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding," in ICASSP, 2007.
T.-Y. Kuo, et al., "A Memory Bandwidth Optimized Interpolator for Motion Compensation " in APCCAS, 2006.
C. C. Cheng, et al., "A Fast Fractional Pel Motion Estimation Algorithm for H.264/MPEG-4 AVC," in VLSICAD, 2005.
Other encoding related papers
C.-C. Lin, et al., "Hardware Efficient Skip Mode Detection for H.264/AVC," in Consumer Electronics, 2008. ICCE 2008. Digest of Technical Papers. International Conference on, 2008, pp. 1-2.
Jian-Long Chen, et al., "A Low Cost Context Adaptive Arithmetic Coder for H.264/MPEG-4 AVC Video Coding," in ICASSP, 2007.
Y. K. Lin, et al., "An area efficient design for integer transform in H.264/AVC FRext," in VLSICAD, 2006.
Intra prediction
Y.-K. Lin and T.-S. Chang, "Fast Block Type Decision Algorithm for Intra Prediction in H. 264 FRExt," in ICIP, 2005, pp. 585-588.
C.-C. Cheng and T.-S. Chang, "Fast three step intra prediction algorithm for 4/spl times/4 blocks in H.264," in ISCAS, 2005, pp. 1509-1512 Vol. 2.
C. C. CHENG, et al., "METHOD AND APPARATUS FOR SELECTING PREDICTION MODE OF INTRA CODING," R. O. C. Patent I301723 2008/10/01, 2008.
Deblocking filter
C.-C. Cheng, et al., "An In-Place Architecture for the Deblocking Filter in H.264/AVC," IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, vol. 53, pp. 530 - 534 July 2006.
C.-C. Cheng and T.-S. Chang, "An hardware efficient deblocking filter for H.264/AVC," in IEEE International Conference on Consumer Electronics, Las Vegas, NV, United States, 2005, pp. 235-236
C. C. CHENG, et al., "DEBLOCK FILTER METHOD FOR APPLYING ON VIDEO ENCODING/DECODING AND THE APPARATUS THEREOF " R. O. C. Patent I264951, 2006/10/21, 2006.
CAVLC Encoder
M.-C. Tsai and T. S. Chang, "A High Performance Context Adaptive Variable Length Coding Encoder " in APCCAS, 2006.
DSP software implementation
H.-C. Lin, et al., "Algorithms and DSP implementation of H.264/AVC," in ASPDAC, 2006, pp. 742-749.
H.264 Decoder
Whole decoder design
G. L. Li, Y. C. Chen, Y. H. Liao, P. Y. Hsu, M. H. Wen, and T. S. Chang, "A 135 MHz 542 k Gates High Throughput H. 264/AVC Scalable High Profile Decoder," Circuits and Systems for Video Technology, IEEE Transactions on, vol. 22, pp. 626-635, 2012.
Motion compensation
N. Y. C. Chang and T. S. Chang, "Combined Frame Memory Motion Compensation for Video Coding," IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, pp. 1280-1285 October 2006.
N. Y. C. Chang and T. S. Chang, "Combined frame memory architecture for motion compensation in video decoding," in ISCAS, 2005, pp. 1806-1809 Vol. 2.
G.-S. Yu and T. S. Chang, "Optimal Data Mapping for Motion Compensation in H.264 Video Decoding," in Signal Processing Systems, 2007 IEEE Workshop on, 2007, pp. 505-508.
T.-S. CHANG and Y.-C. CHANG, "CONTEXT-AWARE FRAME MEMORY SCHEME FOR MOTION COMPENSATION IN VIDEO DECODING " R. O. C. Patent I308459, 2009/04/01, 2009.
CABAC decoder
Y.-H. Liao, G.-L. Li, and T.-S. Chang, "A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder," Circuits and Systems for Video Technology, IEEE Transactions on, vol. 22, pp. 272-281, 2012.
Y.-H. Liao, et al., "A High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoder," in 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 2007-2010.
CAVLC decoder
G. S. Yu and T. S. Chang, "A Zero-Skipping Multi-symbol CAVLC Decoder for MPEG-4 AVC/H.264," in ISCAS, 2006, pp. 5583-5586.
H.264 with scalable extension (SVC)
Y.-C. Chen, et al., "Efficient Inter-layer Predictor Hardware Design with Extended Spatial Scability for H.264/AVC Scalable Extension," in 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 2650-2653.
H.-S. Huang, et al., "Low Memory Bandwidth Prediction Method for H.264/AVC Scalable Video Extension," in Proc. APSIPA ASC, 2009.
P.-Y. Hsu, et al., "Memory Analysis for H.264/AVC Scalable Extension Decoder," in Proc. APSIPA ASC, 2009.
M.-W. Shen, et al., "A Memory Efficient Fine Grain Scalability Coefficient Encoding Method for H.264/AVC Scalable Video Extension," in 2009 IEEE International Symposium on Circuits and Systems, 2009.
T.-Y. Chen, et al., "Memory Analysis for H.264/AVC Scalable Extension Encoder," in 2009 IEEE International Symposium on Circuits and Systems, 2009.
J. B. Huang, et al., "A Display Order Oriented Scalable Video Decoder," in APCCAS, 2006.