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To quote from para 3 of Section 4.3 in the contest rules document - "Slacks are induced either by explicit required arrival time constraints defined in the netlist file, or by implicit setup and hold constraints, that must be considered for every flip-flop in the circuit. The slacks (early, late, or both) should therefore be reported for all the nodes in the fanin cone of any given node for which an explicit or implicit required arrival time constraint must be considered." Kindly elaborate on this.

• A slack must be computed and reported for any node in the netlist where a required arrival time (rat) exists. As an example, if only the late mode rat exists, only the late mode slack should be computed. The rat on a node may exist due to either:
• - an explicit rat assertion on that node from the netlist as mentioned in Section 6.1 of contest rules document v1.0, or
• - required arrival time implicitly computed on the data or clock pin of a flip flop as illustrated in eqns. (32) and (34) in the contest rules document v1.0, or
• - propagated rat: Similar to arrival time propagation (downstream through the netlist), required arrival times should be propagated (upstream through the netlist). Similar to eqns. (1) and (2) in the contest rules document v1.0, given pins A, X, and Y, and assuming edges between pin pairs (A --> X) and (A --> Y), the required arrival time on A is given by:
  • early rat_A = max(early_rat_X - delay_AX, early_rat_Y - delay_AY)
  • late rat_A = min(late_rat_X - delay_AX, late_rat_Y - delay_AY)
  • Note: The above order also denotes the precedence of rat computation. As an example, if a node has an explicit rat assertion, the propagates rat for that node should be ignored. For the clock pin of a flip-flop, the implicit rat computed via the setup and hold constraints should be used instead of the propagated rat. Please see Section 8 of the contest rules document ver1.0 for implementation tips.

A simple expression for the required arrival time at the data input of a flip flop is,

rat = Clock period - setup time

However the Clock period doesn't seem to have been specified ? How can an implicit required arrival time constraint then be derived from the setup and hold time specifications ?

• Please see the rat computation equations (32) and (34) of the contest rules document ver1.0. The clock period is specified for each clock input of the netlist in the netlist file using the keyword "clock". Please refer to Section 6.1 of the contest rules document ver1.0. It should be noted that only sequential circuit netlists are required to have the clock period specified.