Embedded Files
- TAU contest planning document (.ppt) - LINK
- Update from Jia Wang (Oct 26, 2012): I am trying to build a Monte-Carlo based golden quickly and made some progress (thanks to the code from the last contest). So far I can characterize interconnects and load capacitances, as well as build and levelize the timing graph (this seems different from the past code where everything was mixed up). All benchmarks seem good (no cycle as DAG) and the numbers look reasonable. Some graphs are as attached but I do need someone to verify the exact numbers to make sure my understanding is correct. The remaining work is to propagate AT/RAT which should be pretty straight-forward.
- simple.graph:
- in:falling y:falling
- delay(+2.91238e-014, +1.07809e-016 dM) slew(+2.77615e-014, +8.43247e-017 dM)
- in:rising y:rising
- delay(+2.94270e-014, +9.26492e-017 dM) slew(+2.80640e-014, +6.91821e-017 dM)
- y:falling out:falling load_cap(+0.00000e+000, +0.00000e+000 dM) cell(0, AND2_X1)
- slew (+3.77995e-012, +9.76912e+002 L, +1.86390e-002 S, -1.60480e-012 dV, +1.28176e-012 dT, +7.93967e-014 dL, -3.72687e-014 dW, +7.40020e-014 dH, +7.54516e-014 dR)
- delay(+3.70629e-011, +1.24288e+003 L, +2.77092e-001 S, -9.06825e-012 dV, +6.52552e-012 dT, +2.57378e-013 dL, -5.13292e-013 dW, +4.42342e-013 dH, +5.82696e-013 dR)
- y:rising out:rising load_cap(+0.00000e+000, +0.00000e+000 dM) cell(0, AND2_X1)
- slew (+3.39890e-012, +2.26655e+003 L, +4.38529e-003 S, -4.16083e-012 dV, +7.87739e-012 dT, +7.74650e-014 dL, -1.67864e-014 dW, +2.84847e-014 dH, +6.52783e-014 dR)
- delay(+3.65718e-011, +2.39729e+003 L, +1.04169e-001 S, -9.34000e-012 dV, +7.06907e-012 dT, +3.33521e-013 dL, -4.69399e-013 dW, +8.70617e-013 dH, +8.37673e-013 dR)
- z:falling out:falling load_cap(+0.00000e+000, +0.00000e+000 dM) cell(0, AND2_X1)
- slew (+3.76723e-012, +9.81374e+002 L, +1.69389e-002 S, -1.67935e-012 dV, +1.27792e-012 dT, +5.98718e-014 dL, -6.75555e-014 dW, +1.33362e-014 dH, +5.71647e-014 dR)
- delay(+3.97442e-011, +1.24328e+003 L, +2.99300e-001 S, -8.88732e-012 dV, +6.61920e-012 dT, +1.55677e-013 dL, -3.98380e-013 dW, +1.28960e-013 dH, +1.08113e-013 dR)
- z:rising out:rising load_cap(+0.00000e+000, +0.00000e+000 dM) cell(0, AND2_X1)
- slew (+3.32737e-012, +2.26892e+003 L, +3.42535e-003 S, -4.11552e-012 dV, +7.86441e-012 dT, +1.35595e-015 dL, -2.02044e-014 dW, +1.14155e-014 dH, +6.68948e-014 dR)
- delay(+3.55116e-011, +2.40174e+003 L, +9.38833e-002 S, -1.03079e-011 dV, +6.91123e-012 dT, +8.86835e-013 dL, -1.93766e-013 dW, +4.55376e-013 dH, +7.44955e-013 dR)
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