Title: Design and Test of SET Tolerant High Frequency CMOS LC Oscillators
Advisor: Prof. Shalabh Gupta
Abstract:
High energy particle strikes on an integrated circuit (IC) for a communication link degrade its performance leading to data loss in the link. In addition, for wireless links, such strikes lead to generation of spurious spectrum causing interference in other bands. Complementary metal oxide semiconductor (CMOS) ICs used in radiation environments suffer from temporary hazards due to high energy particle strikes known as single-event transient (SET) effects. Techniques to mitigate the SET effects for CMOS ICs used in digital applications have been extensively studied. However, for high frequency ICs designed in deep sub-micron technologies, very limited amount of research work has been carried out. In such technologies, lower supply voltages result in the reduction in voltage amplitudes, because of which, the circuit becomes more vulnerable to small SET induced charges. In addition, high frequency circuits typically have smaller node capacitances. As a result, a given amount of charge induced by an SET event results in a larger change in the node voltage of the high frequency circuits. Therefore, mitigation of the SET effects becomes crucial for proper functioning of high frequency circuits in radiation environments. In RF applications, LC oscillators used for frequency synthesis require special attention as the transients caused by radiation strikes decay slowly due to slow loop dynamics of phase locked loops (PLLs). Often, advanced technology nodes are needed for synthesis of high-frequency signals. In these technologies, as mentioned earlier, smaller capacitances make the high-frequency circuit nodes more vulnerability to SET effects.
In this work, we have designed a wide tuning range LC voltage-controlled oscillator (VCO). The SET effects on this have been studied using circuit simulations with double exponential current pulse, which helps in observing the phase error as a measure of SET tolerance. A trade-off exists between tuning range and SET tolerance in the case of conventional single phase VCOs (SVCOs), which makes them unsuitable for radiation environments. For synthesis of high frequency signals used in such environments, we have proposed the use of quadrature phase LC oscillators. In addition to providing higher tolerance to SETs, these oscillators are also able to provide wider tuning range, which is otherwise difficult to achieve at high frequencies, particularly with low phase noise. To mitigate SET effects on bias transistors of LC oscillators, a distributed biasing technique has been proposed. The charge generated by a radiation strike at the drain of the bias current transistor results in voltage change at the drain node, which causes a reduction in the output impedance of the transistor. This effect is more pronounced in the case of distributed biasing. This phenomenon is exploited for improving radiation tolerance using distributed current bias. The same biasing technique can also be used in other analog circuits, to achieve better SET tolerant designs.
Test of high-frequency CMOS integrated circuits becomes challenging due to complicated setups and limited availability of high-energy particle sources. To emulate radiation strikes and measure SET tolerance of the designed LC oscillators, a pulsed laser based experimental test-bench has been set up. The use of pulsed laser for emulation of radiation strikes is advantageous because it becomes easy to focus the laser spot precisely at desired location on the integrated circuit, and hence provides controlled test environment and repeatability. PLLs with single phase and quadrature phase LC oscillators (using distributed bias current sources) have been designed and fabricated in a CMOS 65 nm LL technology to validate the effectiveness of the proposed techniques. In addition, a test structure to evaluate the SET tolerance of bias transistors has been designed. The test structure helps in evaluating the SET tolerance in terms of the change in voltage corresponding to the SET current generated by the pulsed laser. Finally, it is shown that the experimental results obtained from the laser based test setup for these oscillators and bias circuits validate the theories and techniques that have been developed in this work.