About

I, Sharayu J., am a Research Associate at Communications Lab, Indian Institute of Technology (IIT) Bombay. I am currently involved in a team working on design, layout, and test of serializer-deserializer. I am a recent graduate from Department of Electrical Engineering, Indian Institute of Technology Bombay. My PhD advisor was Prof. Shalabh Gupta.

My Ph.D. topic is Design and Test of SET Tolerant High Frequency CMOS LC Oscillators. High frequency circuits are sensitive to single event transient (SET) effects, which degrade circuits' performance especially in scaled CMOS technologies. In this work, new design techniques are proposed to improve SET tolerance of high frequency oscillators. I have successfully designed and tested the test chips (includes voltage-controlled oscillators and phase-locked loops) employing the design techniques proposed by us. I am initiator of pulsed laser based test setup to evaluate SET effects on Integrated Circuits (ICs) at Communications Laboratory, Department of Electrical Engineering. Experimental results clearly validate the effectiveness of the techniques proposed for improving SET tolerance in high frequency oscillators. Abstract of my research work is here.

I am currently reside in Mumbai. I obtained a Master's degree in Electronics Engineering from Veermata Jijajbai Institute of Technology (VJTI), Mumbai in year 2009. I obtained a Bachelor's degree from Datta Meghe College of Engineering (DMCE), Mumbai in year 2006 and completed a final year project from Tata Institute of Fundamental Research (TIFR) in a team of four students.

Apart from my research passion, I am interested in trekking and Indian classical music. I have pursued this in:

• Trekking and mountain biking with nationally recognized organization: Youth Hostel Association of India (YHAI).
• First class in three examination of Hindustani classical music (vocal) conducted by Akhil Bharatiya Gandharva Mahavidyalaya Mandal.