arch-asg7

Assignment 7

Memory Hierarchies:  Cache and Virtual Memory

Due: By the final exam

In the book.  (10 points)

Chapter 5:  5.2 (only parts 1-3), 5.3, 5.5, 5.7, 5.11 (only parts 1-4), 5.13.

1.     This problem puts everything together:  Virtual memory, set associative TLB, and direct mapped multi-byte block cache.  It is an important example to understand and practice. 

Refer to the Page table, TLB, and Cache table below to answer these questions. 

Note the standard practice, as used in this example below, is that valid = 1 means that the data is in RAM, and valid = 0 means a page fault.

What would happen if a CPU tries to access the following virtual addresses? 

a)      0x0364 

b)     0x033D

c)     0x036B

For each case:  Is there a TLB hit or miss? Is there a cache hit or miss?  What is the result of the memory access or is there a page fault?

Addressing

  14-bit virtual address

  12-bit physical address

Page size = 64 bytes