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Digital VLSI design for Wireless Communications
Digital VLSI design for Wireless Communications
Digital very large scale integration (VLSI) design is one of my key research areas. We aim to develop high performance and energy efficient digital circuits for ASICs and FPGAs. Currently most of my use cases are related to wireless communication applications.
Some Publications:
1. S. Shahabuddin, I. Hautala, M. Juntti, and C. Studer, "ADMM-based Infinity Norm Detection for Massive MIMO: Algorithm and VLSI Architecture", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2021.
2. S. Shahabuddin, M. A. Albreem, M. S. Shahabuddin, Z. Khan, and M. Juntti, ”FPGA Implementation of Stair Matrix based Massive MIMO Detection”, IEEE Latin America Symposium on Circuits and System (LASCAS), 2021.
You can find more on digital VLSI designs for ASIC/FPGA here:
Fig. Circuit diagrams and ASIC layout of massive MIMO detector
Digital and Multirate Signal Processing
Digital and Multirate Signal Processing
I am actively working on digital and multirate signal processing. Fundamental DSP research is required for advanced channel filtering, sample rate converter, crest factor reduction and pre-distortion which are widely used in different domains.
Some Publications:
1. A. Ghazi, J. Boutellier, L. Anttila, S. Bhattacharya, S. Shahabuddin, M. Juntti, and O. Silven, “Model-based Design and Implementation of an Adaptive Digital Predistortion Filter", 2015 IEEE Workshop on Signal Processing Systems, China.
Fig. A 400 MHz sample rate converter output
Machine Learning for Wireless Communications
Machine Learning for Wireless Communications
Machine learning has been one of my key research topics over the past few years. We explored the use cases, opportunities and challenges of machine learning algorithms for wireless communications. The sustainability of AI will be a key research topic for many years to come. Therefore, novel low-complexity machine learning algorithms will continue to be one of my key focus area.
Some Publications:
1. I. Ahmad, S. Shahabuddin, H. Malik, E. Harjula, T. Leppanen, L. Loven, A. Anttonen, A. H. Sodhro, M. M. Alam, M. Juntti, A. Yla-Jaaski, A. Gurtov, T. Sauter, J. Riekki and M. Ylianttila, "Machine Learning Meets Communication Networks: Existing Trends and Future Challenges", IEEE Access, December 2020.
2. I. Ahmad, S. Shahabuddin, T. Kumar, E. Harjula, M. Meisel, M. Juntti, T. Sauter, and M. Ylianttila, "The Challenges of Artificial Intelligence in Wireless Networks for the Internet of Things: Exploring Opportunities for Growth", IEEE Industrial Electronics Magazine, December 2020.
Wireless Network Security
Wireless Network Security
I have been also actively working on the 5G and 6G Security fields. Security and privacy has become one of the most important requirements for 5G and post-5G telecom research. We will continue to work on such a promising domain.
Some Publications:
1. I. Ahmad, S. Shahabuddin, T. Kumar, J. Okwuibe, A. Gurtov and M. Ylianttila, "Security for 5G and Beyond", in IEEE Communications Surveys and Tutorials, vol. 21, no. 4, pp. 3682-3722, Fourth quarter 2019.
2. L. Mucchi, A. Martinelli, S. Jayousi, S. Caputo, E. Panayirci, H. Haas, S. Shahabuddin, J. Bechtold, I. Morales, A. Stoica, and G. Abreu, ”Physical-layer security in 6G Networks”, in IEEE Open Journal of the Communications Society, August 2021.
Fig. A system model of intelligent reflective surface security
Algorithm Design for Advanced MIMO Transceivers
Algorithm Design for Advanced MIMO Transceivers
MIMO systems have been continuously evolving to accommodate the high data rate requirements of modern wireless systems. With the introduction of every novel MIMO systems, we need to design or re-design transmitter and receivers to utilize their full potential. Therefore, algorithm design for MIMO transceivers will continue to be one of my key research topic.
Some Publications:
1. S. Shahabuddin, J. Janhunen, A. Ghazi, Z. Khan, and M. Juntti, “A Customized Lattice Reduction Multiprocessor for MIMO Detection", in IEEE International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal, May 2015.
2. S. Shahabuddin, M. Juntti, and C. Studer, "ADMM-based Infinity Norm Detection for Large MU-MIMO: Algorithm and VLSI Architecture", in IEEE International Symposium on Circuits and Systems, Maryland, USA, May 2017.
Fig. An algorithm for lattice reduction
Machine Learning Accelerator Design
Machine Learning Accelerator Design
Machine learning accelerator design will be one of my key research areas in the future. As the optimized machine learning solutions are distinct for each domains and applications, there will be a massive need of designing accelerators to fulfil the performance and cost requirements. We will combine our digital VLSI, signal processing and machine learning expertise for this domain.
Some Publications:1. S. Shahabuddin, Z. Khan, and M. Juntti, "Concept Drift Detection Methods For Deep Learning Cognitive Radios: A Hardware Perspective", in IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
Fig. Chi-square statistics computation unit for concept drift detection between deep learning models
Application-specific processors (ASIP) Design
Application-specific processors (ASIP) Design
Application-specific processors (ASIP) is an alternative to conventional digital VLSI systems. The ASIPs are typically more costly than conventional VLSI systems, but provides more flexibility because they are programmable with high level software such as C/C++. We are interested in ASIP designs based on transport triggered architectures (TTA) for wireless communications, machine vision and other applications.
Some Publications:
1. S. Shahabuddin, O. Silven, and M. Juntti, "ASIP design for Multiuser MIMO Broadcast Precoding", European Conference on Networks and Communications (EUCNC), Oulu, Finland, June 2017.
2. S. Shahabuddin, J. Janhunen, M. F. Bayramoglu, M. Juntti, A. Ghazi, and O. Silven, "Design of a unified transport triggered processor for LDPC/turbo decoder", in 13th International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation, Samos, Greece, July 2013.
More on application specific processors can be found here:
A TTA processor design with the TCE tool
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