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Energy Efficient and High Throughput Canonical Huffman Codec Designs
Canonical Huffman Decoder (ASP-DAC 2021)
Canonical Huffman codecs have been used in a wide variety of platforms ranging from mobile devices to data centers which all demand high energy efficiency and high throughput. This work presents bit-parallel canonical Huffman decoder implementations on a fine-grain many-core array built using simple RISC-style programmable processors. We develop multiple energy-efficient and area-efficient decoder implementations and the results are compared with an Intel i7-4850HQ and a massively parallel GT 750M GPU executing the corpus benchmarks: Calgary, Canterbury, Artificial, and Large. The many-core implementations achieve a scaled throughput per chip area that is 324x and 2.7x greater on average than the i7 and GT 750M respectively. In addition, the many-core implementations yield a scaled energy efficiency (bytes decoded per energy) that is 24.1x and 4.6x greater than the i7 and GT 750M respectively.
DeepScaleTool : A Tool for Accurate Estimation of Technology Scaling in Deep-submicron Era
DeepScaleTool is a spreadsheet based tool for the accurate estimation of deep-submicron technology (130 nm to 7 nm) scaling by modeling and curve fitting published silicon trends for area, delay, and energy. The tool is also helpful to conduct fair comparison of the circuits' performance, energy, and power dissipation across different technology generations.
Download link - https://sourceforge.net/projects/deepscaletool/ (ISCAS 2021)
Doctoral Student Researcher (09/2014 - Present)
Mentor: Prof. Bevan Baas , Professor, Department of ECE, UC Davis ; Lab : VLSI Computation Lab
Asynchronous Array of Simple Processors (AsAP) and Applications
Laboratory Video Display Application
Energy Efficient and high Throughput Canonical Huffman Codecs
Gzip accelerator design
Scaling estimations for various performance metrics from 130-nm to 7-nm
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Key Academic Projects during Doctoral Coursework (09/2014 - 03/2016)
Study of Map-Reduce and implementation of inverted indexing on Hadoop (Operating Systems)
Full custom chip layout of some of the important blocks of CAVLC entropy coder (Layout Design)
RTL design, synthesis and verification for CDMA transmitter blocks (ASIC)
FPGA implementation of dynamic programming and Bloom filter (FPGA)
Design of improved router for buffer less on-chip network (High Performance Computer Architecture)
Matrix multiplication and Eigen vector computation kernels on Stampede supercomputer (High Performance Computing)
Energy efficient 32-bit adder design at sub-threshold regime (VDD ~400 mV) running at 100 MHz (Low Power Digital IC Design)
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Graduate Student Researcher (Master's) (09/2011 - 06/2014)
Mentor: Prof. Swapna Banerjee, Professor , Department of ECE, IIT Kharagpur ; Lab : VLSI CAD Lab
Hardware Implementation of Encoder and Decoder for Golay Code
This work lays out cyclic redundancy check-based encoding scheme and presents an efficient implementation of encoder and decoder for Golay code.
Study of Golay Coded Excitation on Photo acoustics Spectroscopy
This work presents a method for improvement in SNR and resolution of photo acoustic (PA) signal using Golay coded excitation for a non-invasive and continuous glucose monitoring.
Non-Invasive Glucose Monitoring System
This work aims at designing a non-invasive glucose monitoring system using photo acoustic spectroscopy.
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Under-Graduate Project (01/2011 - 04/2011)
Mentor: Mr. Giridhari Muduli and Dr. Jitendra Kumar Das, Department of Electronics and Telecommunication Engineering, Synergy Institute of Engg. and Technology
Microcontroller based temperature controller
Circuit level implementation of amplitude modulator and demodulator
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