Industry Experience

ASIC Design Engineer, Meta Platforms, Inc., Sunnyvale, CA, Sept'22 - Present

• Micro-architecture and Design of Video Transcoding and AI/ML HW Accelerators

SoC Architecture and Logic Design Intern, Intel Corporation, Hillsboro, OR, June'19 - September'19

• Conducted architectural analysis of an accelerator and SoC. 

• Developed a mechanism to speed-up verification of the correct bitstream configuration of the chip per the architecture rules.

• Executed Architecture, RTL design, implementation and formal verification of the BF16 floating point arithmetic blocks. 

Product Engineer Intern, Intel Corporation, San Jose Innovation Center, CA, August'17 - March'18

• Power modeling for next generation and high end Intel FPGAs

• Power (Static/Dynamic/Thermal) analysis, optimizations and debug

• Used CMT and ATE test set-ups and other laboratory tools for silicon power measurements 

• Power correlations and Power - Performance - Yield trade off 

Graduate Research Intern, TCS Innovation Lab, Kolkata, October'13 - Jan'14

• Feature extraction algorithms for bio-medical signals 

• Investigation on non-invasive techniques for various physiological parameters using photo acoustic spectroscopy