Satyabrata is currently working as an ASIC Design Engineer with Meta (formerly Facebook) on video transcoding and AI/ML hardware accelerators. He earned his Ph.D. from Department of Electrical & Computer Engineering, University of California Davis (UC Davis) with a major in VLSI Design and Computer Systems (Class of 2022) under the guidance of Prof. Bevan Baas. He completed Master's (MS Thesis Plan) with a major in VLSI Design (Class of 2014) from Indian Institute of Technology Kharagpur under the guidance of Prof. Swapna Banerjee and Bachelor's with a major in Electronics and Telecommunication Engineering (Class of 2011) from Biju Patnaik University of Technology. 

Satyabrata worked as a Graduate Student Researcher in VLSI Computation Lab under the guidance of Prof. Bevan Baas. His primary areas of interests include:

• Many-core Processor Architecture and Data Compression Accelerators

• Low Power Digital VLSI Design

• Power-Performance Modeling and Optimizations

• FPGAs and ASIC Design 

• Bio-Medical Instrumentation

Please look around to know more about his research and professional activities.