- Implementation of GS320 directory based cache coherence protocol on a multiprocessor (SIMICS/GEMS).
- Implementation of microarchitectural L2 miss latency techniques (Continual flow pipelines, Checkpointed early load retirement and run ahead execution, Simulator: SimpleScalar).
- Implementation of a trace based cache simulator and studying various cache replacement policies (Language: C).
- Implementation of various branch predictors (gselect, two–level and hybrid, Language: C).
- Implementation of Superscalar pipeline simulator: Implemented a simulator for an out-of-order superscalar processor based on Tomasulo’s algorithm that fetches and executes N instructions per cycle (Language: C).
- Implementation of a C to S3 (A simplified instruction set) compiler, which included parsing, scalar optimizations and VLIW Scheduling (Language: C).
- Parallelization of programs for a shared memory parallel machine using OpenMP.
- Implementation of MSI protocol for maintaining cache coherence for a multiprocessor (SESC).
- Implementation of a user level thread library (Language: C).
- Implementation of a microshell which implements standard unix commands, redirection of input/output and pipes (Language: C).
- Implementation of a distributed game of “hot potato” using sockets and TCP/IP communication (Language: C).
- Implementation of a Distributed File system using FUSE (Language: C).
- Implementation of a Hardware Sudoko Solver (Language: Verilog HDL).
- Design and Layout of 128 bit SRAM based on 45nm process node.