Publications

112.  G. Borin, A. Marelli and R. Micheloni, “Towards more precise and reliable estimations of the capacity of DNA storage channels”, White Paper, www.dnaalgo.com, January, 2024. 

111. M. Borghesi, C. Zambelli, R. Micheloni, and S. Bonnini, " Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage", Future Internet 2023, 15(10), 319; https://doi.org/10.3390/fi15100319. 

110. (Invited) R. Micheloni, A. Marelli, "Un’applicazione futuristica dei codici a correzione di errore: la memorizzazione dei dati digitali su DNA sintetico", Cryptography and Coding Theory Conference, Perugia, Italy, September 21-22, 2023. 

109.  M. Montana, A. Marelli, R. Micheloni, V. De Cian, C. Spolaore, C. Tocalli, "DNAe2c ECC for DNA Data Storage: 10x Improvement over RS Codes", Storage Developer Conference, Fremont, CA, USA, Sep. 18-21, 2023. 

108. G. Minghini, A. U. Cavallo, A. Miola, V. Sisini, E. Calore, F. Fortini, R. Micheloni, P. Rizzo, S. F. Schifano, F. Vieceli Dalla Sega, and C. Zambelli, "An HPC pipeline for Calcium Quantification of Aortic Root from Contrast-Enhanced CCT Scans" in IEEE Access, doi: 10.1109/ACCESS.2023.3315734. Sept, 2023. 

107. C. Zambelli, A. Miola, E. Calore, R. Micheloni, S. Schifano, “Computational Storage for 3D NAND Flash Error Recovery Flow Prediction”, Poster Session II, SIE Meeting, Noto, Italy, September 6-8, 2023.

106. A. Marelli, T. Chiozzi, N. Battistini, L. Zuolo, R. Micheloni, C. Zambelli, “Integrating FPGA Acceleration in the DNAssim Framework for Faster DNA-Based Data Storage Simulations”, Electronics 2023, 12(12), 2621. June, 2023. https://doi.org/10.3390/electronics12122621.

105. M. Pesic, B. Beltrando, T. Rollo, C. Zambelli, A. Padovani, R. Micheloni, R. Maji, L. Enman, M. Saly, Y.H. Bae, J.B. Kim, D. K. Yim, L. Larcher, "Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND", Proceedings of the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, March 26-30, 2023.

104. A. Marelli, T. Chiozzi, L. Zuolo, N. Battistini, P. Olivo, C. Zambelli, R. Micheloni, "DNAssim: A Full System Simulator for DNA Storage", Storage Developer Conference, Fremont, CA, USA, Sep. 12-15, 2022. 

103. A. Marelli, T. Chiozzi, L. Zuolo, N. Battistini, G. Lanzoni, P. Olivo, C. Zambelli, R. Micheloni, "DNAssim: A Full System Simulator for DNA Storage", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 2-4, 2022.

102. (Invited) R. Micheloni, C. Zambelli, "Machine Learning and Non-Volatile Memories", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 2-4, 2022.

101. C. Zambelli, R. Micheloni, “Editorial for the Special Issue on Flash Memory Devices”, Micromachines 2021, 12, 1152. Special Issue "Flash Memory Devices". https://doi.org/10.3390/mi12121566.

100. C. Zambelli, L. Crippa, R. Micheloni, P. Olivo, "Investigating 3D NAND Flash Read Disturb Reliability with Extreme Value Analysis", IEEE Transaction on Device and Materials Reliability, Early Access Aug. 2021.

99. M. Favalli, C. Zambelli, A. Marelli, R. Micheloni, P. Olivo, “A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories”, Micromachines 2021, 12, 759. Special Issue "Flash Memory Devices". https://doi.org/10.3390/mi12070759.

98. C. Zambelli, L. Zuolo, A. Aldarese, S. Scommegna, R. Micheloni, P. Olivo, "Assessing the Role of Program Suspend Operation in 3D NAND Flash Based Solid State Drives". Electronics 2021, 10, 1394. Special Issue "High-Density Solid-State Memory Devices and Technologies". https://doi.org/10.3390/electronics10121394 . 

97. M. Rowshan, E. Viterbo, R. Micheloni, A. Marelli, “Logarithmic Non-uniform Quantization for List Decoding of Polar Codes”, IEEE Computing and Communication Workshop and Conference (CCWC), Virtual Conference, Jan. 27-30, 2021.

96. C. Zambelli, L. Crippa, R. Micheloni, P. Olivo, "Points-Over-Threshold Statistics for Post-Retention Read Disturb Reliability in 3D NAND Flash Memories", IEEE International Integrated Reliability Workshop (IIRW), Virtual Conference, Oct. 2020.

95. C. Zambelli, L. Zuolo, L. Crippa, R. Micheloni, P. Olivo, "Mitigating Self-Heating in Solid State Drives for Industrial Internet-of-Things Edge Gateways" Electronics (MDPI) 9, no. 7, 1179, July, 2020.

94. L. Zuolo, R. Micheloni, C. Zambelli, P. Olivo, " An FPGA-based Neural Network Accelerator for Computational Storage Platforms", Proceedings of the Embedded World Conference, Nuremberg, Germany, Feb. 25-27, 2020.

93. C. Zambelli, R. Micheloni, S. Scommegna, P. Olivo “First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting from an Idle State”, IEEE Journal of the Electron Devices Society, Vol. 8, 2020.

92. V.B. Wijekoon, E. Viterbo, Y. Hong, R. Micheloni, A. Marelli, “A Novel Graph Expansion and a Decoding Algorithm for NB-LDPC Codes”, IEEE Transactions on Communications, Volume 8, Issue 3, pp. 1358-1369, March, 2020.

91. C. Zambelli, E. Ferro, L. Crippa, R. Micheloni, P. Olivo, "Dynamic VTH Tracking for Cross-Temperature Suppression in 3D-TLC NAND Flash”, Proceedings of the International Integrated Reliability Workshop (IEEE-IIRW), Fallen Leaf Lake, CA, USA, October 13-17, 2019.

90. C. Zambelli, R. Micheloni, P. Olivo, "Reliability Challenges in 3D NAND Flash memories”, Reliability Experts Forum, International Integrated Reliability Workshop (IEEE-IIRW), Fallen Leaf Lake, CA, USA, October 13-17, 2019.

89. C. Zambelli, R. Bertaggia, L. Zuolo, R. Micheloni, P. Olivo, "Enabling Computational Storage through FPGA Neural Network Accelerator for Enterprise SSD”, International Symposium on Integrated Circuits and Systems (ISICAS), Venice, Italy, August 29-30, 2019.

88. V. Wijekoon, E. Viterbo, Y. Hong, S. Liu, R. Micheloni, A. Marelli, “Coset Probability based Majority-logic Decoding for Non-binary LDPC Codes”, Poster Session, IEEE Information Theory Workshop (ITW), Visby, Gotland, Sweden, August 25-28, 2019.

87. R. Micheloni, S. Scommegna, A. Aldarese, L. Crippa, "Characterization of 3D NAND Flash Memories beyond 1GT/s ", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 6-8, 2019.

86. R. Micheloni, L. Zuolo, "Improving Quality of Service for 3D NAND SSDs Using LDPC Correction", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 6-8, 2019.

85. C. Zambelli, A. Marelli, R. Micheloni, "Intra-disk RAID for Extreme Data Recovery", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 6-8, 2019.

84. C. Zambelli, R. Bertaggia, L. Zuolo, R. Micheloni, P. Olivo, " Enabling Computational Storage through FPGA Neural Network Accelerator for Enterprise SSD”, IEEE Transactions on Circuits and Systems II, Express Briefs, 2019.

83. (Invited) C. Zambelli, R. Micheloni, P. Olivo, "Reliability Challenges in 3D Nand Flash Memories", Proceedings of the IEEE International Memory Workshop (IMW), Monterey, CA, USA, May 13-15, 2019.

82. S. Liu, Y. Hong, E. Viterbo, A. Marelli, R. Micheloni, “Efficient Decoding of Low Density Lattice Codes”, IEEE Wireless Communications Letters, April, 2019.

81. M. Rowshan, E. Viterbo, R. Micheloni, A. Marelli, "A Stepped List Decoder for Polar Codes", Poster Session, Non-Volatile Memory Workshop (NVMW), San Diego, CA, USA, March 10-12, 2019.

80. L. Zuolo, M. Cirella, A. Marelli, R. Micheloni, " SSD SoC Microcontroller with Embedded Neural Network for 3D NAND Flash Memories ", Proceedings of the Embedded World Conference, Nuremberg, Germany, Feb. 26-28, 2019.

79. M. Rowshan, E. Viterbo, R. Micheloni, A. Marelli, "Repetition-assisted decoding of polar codes", Electronics Letters, IET (The Institution of Engineering and Technology) Digital Library, January, 2019.

78. R. Micheloni, "Scaling and Reliability challenges of 3D NAND Flash memories", Proceedings of the 16th International System-on-Chip (SoC) Conference, University of California, Irvine (UCI), CA, USA, Oct. 17-18, 2018.

77. (Invited) C. Zambelli, R. Micheloni, "Reliability of NVM in Solid State Drives: a cross-layer approach", International Integrated Reliability Workshop (IEEE-IIRW), Fallen Leaf Lake, CA, USA, October 7-11, 2018.

76. C. Zambelli, L. Crippa, R. Micheloni, P. Olivo, "Cross-Temperature Effects of Program and Read Operations in 2D and 3D NAND Flash Memories”, Proceedings of the International Integrated Reliability Workshop (IEEE-IIRW), Fallen Leaf Lake, CA, USA, October 7-11, 2018.

75. L. Zuolo, A. Marelli, R. Micheloni, "Fully Integrated LLR Calculation Flow", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 7-9, 2018.

74. L. Zuolo, M. Cirella, A. Marelli, R. Micheloni, "A Machine Learning Framework for NAND Flash Lifetime Extension", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 7-9, 2018.

73. C. Zambelli, R. Micheloni, L. Crippa, L. Zuolo, P. Olivo, "Impact of the NAND Flash Power Supply on Solid State Drives Reliability and Performance”, IEEE Transactions on Device and Materials Reliability, Volume 18, Issue 6, pp. 247-255, June, 2018.

72. R. Micheloni, "Memory-Driven Design Methodologies For Solid State Drives (SSDs)", PhD Thesis, University of Ferrara, Feb. 2018.

71. R. Micheloni, " Flash Controllers for SSD’s Lifetime Extension through Machine Learning", Proceedings of the 15th International System-on-Chip (SoC) Conference, University of California, Irvine (UCI), CA, USA, Oct. 18-19, 2017.

70. C. Zambelli, A. Marelli, R. Micheloni, P. Olivo, "Modeling the Endurance Reliability of Intra-disk RAID Solutions for mid-1X TLC NAND Flash Solid State Drives”, IEEE Transactions on Device and Materials Reliability, Volume 17, Issue 4, pp. 713-721, December, 2017.

69. R. Micheloni, "3D Nand Flash Memories: Array Architectures and Scaling/Reliability Challenges", Proceedings of the Non-Volatile Memory Technology Symposium (NVMTS), Aachen, Germany, Aug. 30 -Sept. 1, 2017.

68. R. Micheloni, P. Olivo, “Solid-State Drives (SSDs) [Scanning the Issue]”, Proceedings of the IEEE, Volume 105, Issue 9, pp. 1586-1588, September, 2017. 

67. (Invited) L. Zuolo, C. Zambelli, R. Micheloni, P. Olivo, “Solid-State Drives: Memory Driven design Methodologies for Optimal Performance”, Proceedings of the IEEE, Volume 105, Issue 9, pp. 1589-1608, September, 2017.

66. (Invited) R. Micheloni, S. Aritome, L. Crippa, “Array architectures for 3-D NAND Flash Memories”, Proceedings of the IEEE, Volume 105, Issue 9, pp. 1634-1649, September, 2017.

65. R. Micheloni, L. Crippa, C. Zambelli, P. Olivo, "Architectural and Integration Options for 3D NAND Flash Memories”, MDPI Computers, Special Issue on “3D Flash Memories”, 6(3), 27, doi: 10.3390/computers6030027, 2017.

64. L. Zuolo, C. Zambelli, A. Marelli, R. Micheloni, P. Olivo, "LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives”, IEEE Transactions on Emerging Topics in Computing, 2017.

63. C. Zambelli, L. Zuolo, P. Olivo, L. Crippa, A. Marelli, R. Micheloni, "Characterization of Uniform and Concentrated Read Disturb Effect in Mid-1X TLC NAND Flash Memories", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 8-10, 2017. 

62. L. Zuolo, C. Zambelli, T. Hulett, B. Cooke, R. Micheloni, P. Olivo, "IOPS and QoS Analysis of DRAM-based and MRAM-based NVRAM Cards", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 8-10, 2017. 

61. R. Micheloni, A. Marelli, "SSD Lifetime Extension using Multi-Code-Rate LDPC with Multi-Dimensional LLR", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 8-10, 2017. 

60. C. Zambelli, G. Cancelliere, F. Riguzzi, E. Lamma, P. Olivo, A. Marelli, and R. Micheloni, "Characterization of TLC 3D-NAND Flash Endurance through Machine Learning for LDPC Code Rate Optimization", Proceedings of the IEEE International Memory Workshop (IMW), Monterey, CA, USA, May 14-17, 2017.

59. R. Micheloni, "Solid-State Drive (SSD): A Nonvolatile Storage System”, Point Of View, Proceedings of the IEEE, Volume 105, Issue 4, pp. 583-588, April, 2017.

58. C. Zambelli, P. Olivo, L. Crippa, A. Marelli, and R. Micheloni, "Uniform and Concentrated Read Disturb Effects in Mid-1X TLC NAND Flash Memories for Enterprise Solid State Drives", Proceedings of the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, Apr. 2-6, 2017.

57. L. Zuolo, C. Zambelli, T. Hulett, B. Cooke, R. Micheloni, P. Olivo, " IOPS and QoS Analysis of DRAM/Flash-based and All-MRAM based NVRAM cards", Non-Volatile Memory Workshop (NVMW), San Diego, CA, USA, March 12-14, 2017.

56. L. Zuolo, M. Cirella, C. Zambelli, R. Micheloni, P. Olivo, "Simulation platform for sub-10us RRAM-based Solid State Drives", Poster Session, Open Power Summit Europe, Barcelona, Spain, Oct. 26-28, 2016. 

55. R. Micheloni, "Impact of 3D Flash Memories on SSD's Controller Design", Proceedings of the 14th International System-on-Chip (SoC) Conference, University of California, Irvine (UCI), CA, USA, Oct. 19-20, 2016. 

54. L. Zuolo, M. Cirella, C. Zambelli, R. Micheloni, P. Olivo, "Performance Assessment of an All-RRAM Solid State Drive Through a Cloud-Based Simulation Framework", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 8-11, 2016. 

53. A. Marelli, R. Micheloni, "False Decoding Probability (Detection) of BCH and LDPC Codes", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 8-11, 2016. 

52. L. Zuolo, C. Zambelli, A. Grossi, P. Olivo, R. Micheloni, S. Bates, "Memory System Architecture Optimization for Enterprise All-RRAM Solid State Drives", Proceedings of the IEEE International Memory Workshop (IMW), Paris, France, May 15-18, 2016. 

51. C. Zambelli, P. King, P. Olivo, L. Crippa and R. Micheloni, "Power-Supply Impact on the Reliability of mid-1X TLC NAND Flash Memories", Proceedings of the 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, Apr. 17-21, 2016. 

50. L. Zuolo, M. Cirella, C. Zambelli, R. Micheloni, S. Bates, P. Olivo, "Performance Assessment of an All-RRAM Solid State Drive through a Cloud-Based Simulation Framework", Poster Session, Non-Volatile Memory Workshop (NVMW), San Diego, CA, USA, March 6-8, 2016. 

49. L. Zuolo, C. Zambelli, R. Micheloni, S. Bates, P. Olivo, "Design Space Exploration of Latency and Bandwidth in RRAM-based Solid State Drives ", Poster Session, Non-Volatile Memory Technology Symposium (NVMTS), Tsinghua University, China, Oct. 11-14, 2015. 

48. R. Micheloni, A. Marelli, L. Crippa, A. Aldarese, "Fully Integrated NAND-SSD Characterization Flow", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 11-13, 2015. 

47. K. Zhao, R. Micheloni, T. Zhang, "Safely Overclocking Flash I/O in SSDs", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 11-13, 2015. 

46. L. Zuolo, C. Zambelli, R. Micheloni, P. Olivo, "SSDExplorer: A virtual platform for SSD simulation", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 11-13, 2015. 

45. L. Zuolo, C. Zambelli, P. Olivo, R. Micheloni, A. Marelli, "LDPC Soft Decoding with Reduced Power and Latency in 1X-2X NAND Flash-Based Solid State Drives", Proceedings of the International Memory Workshop (IMW), Monterey, CA, USA, April, 2015.

44. L. Zuolo, C. Zambelli, R. Micheloni, S. Galfano, M. Indaco, S. Di Carlo, P. Prinetto, P. Olivo, D. Bertozzi, "SSDExplorer: a Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April, 2015.

43. L. Zuolo, C. Zambelli, R. Micheloni, S. Bates, P. Olivo, "Quality of Service Implications of the Error Correction Techniques in Solid State Drives", Poster Session, Non-Volatile Memory Workshop (NVMW), San Diego, CA, USA, March 1-3, 2015.

42. K. Zhao, J. Li, J. Ma, R. Micheloni, T. Zhang, "Overclocking NAND Flash Memory IO Link in LDPC-based SSDs", IEEE Transactions on Circuits and Systems II, Express Briefs, Volume PP, Issue 99, August, 2014.

41. R. Micheloni, P. Graumann, "Hardware/Software Co-Simulation for Error-Floor Detection in LDPC", Proceedings of the Flash Memory Summit, www.flashmemorysummit.com, Santa Clara, CA, USA, Aug. 5-7, 2014.

40. S. Bates, A. Marelli, R. Micheloni, "Error Correction Control for Next-Generation Solid State Drives", White Paper, www.microsemi.com, July, 2014.

39. L. Zuolo, C. Zambelli, R. Micheloni, D. Bertozzi and P. Olivo, "Analysis of Reliability/Performance Trade-off in Solid State Drives", Proceedings of the 2014 IEEE International Reliability Physics Symposium (IRPS), pp. 4B.3.1 – 4B.3.5, Hawaii, USA, June 1-5, 2014.

38. L. Zuolo, C. Zambelli, R. Micheloni, S. Galfano, M. Indaco, S. Di Carlo, P. Prinetto, P. Olivo, D. Bertozzi, "SSDExplorer: a Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives", Proceedings of Design, Automation and Test in Europe (DATE), Dresden, Germany, pp. 1-6, March 24-28, 2014.

37. R. Micheloni, "8 GT/s PCIe Digital Retimer Implementation", PCI-SIG Developers Conference, Tel Aviv, Israel, March 12, 2013.

36. R. Micheloni, "SSDs in the Cloud Computing Era: PCI Express Interface and NVMe", Automotive Forum, Electronica 2012, Munich, Germany, Nov. 14, 2012.

35. R. Micheloni et al., "Flash Characterization Flow for Enterprise SSDs", 2011 IDT Technical Leadership Forum (TLF), Santa Clara, CA, USA, September, 2011.

34. A. Marelli, R. Micheloni, P. Onufryk, "RAID and ECC for Enhanced Reliability", 2011 IDT Technical Leadership Forum (TLF), Santa Clara, CA, USA, September, 2011.

33. R. Micheloni et al., "Flash Management Algorithms for Enterprise Class SSDs", 2010 IDT Technical Leadership Forum (TLF), Santa Clara, CA, USA, September, 2010.

32. A. Marelli, R. Micheloni, "ECC Engine for Enterprise Class SSDs", 2010 IDT Technical Leadership Forum (TLF), Santa Clara, CA, USA, September, 2010.

31. (Invited) R. Micheloni, M. Picca, S. Amato, H. Schwalm, M. Scheppler, S. Commodaro, “Non Volatile Memories for Removable Media”, Proceedings of the IEEE, Volume 97, Issue 1, pp. 148-160, January, 2009.

30. (Invited) T. Zhang, R. Micheloni, G. Zhang, Z. R. Huang, J. Q. Lu, “3'D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration from System Design Perspectives”, Proceedings of the IEEE, Volume 97, Issue 1, pp. 161-174, January, 2009.

29. G. Campardo, G. Ripamonti, R. Micheloni, “3-D Integration Technologies [Scanning the Issue]”, Proceedings of the IEEE, Volume 97, Issue 1, pp. 5-8, January, 2009.

28. G. Campardo, R. Micheloni, "La rivoluzione delle memorie", Le scienze (Scientific American - Italian version), pp. 104-110, August, 2007.

27. R. Micheloni et al., “A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput”, Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 497-506, February, 2006.

26. A. Marelli, R. Micheloni, R. Ravasio, book "Error Correcting Codes for Flash Memories", Industry Days 2003-2004" edited by D. Aquilano et al., Societa' Editrice Esculapio, pp. 57-61, 2005.

25. A. Cabrini, R. Micheloni, O. Khouri, S. Gregori, G. Torelli, “High input range sense comparator for multilevel flash memories”, Proceedings of the IEEE International Symposium on Circuits & Systems (ISCAS), Vol. 2, pp. 657-660, May 23-26, 2004.

24. (Invited) R. Micheloni, L. Crippa, M. Sangalli, G. Campardo, “The flash memory read path: building blocks and critical aspects”, Proceedings of the IEEE, Volume 91, Issue 4, pp. 537-553, April, 2003.

23. A. Marelli, R. Micheloni, R. Ravasio, "Error correcting codes for flash memories", Poster Session, Coding & Cryptography Workshop, Milan, December, 2003.

22. (Invited) I. Motta, G. Ragone, O. Khouri, G. Torelli, R. Micheloni, “High-voltage management in single-supply CHE nor-type flash memories”, Proceedings of the IEEE, Volume 91, Issue 4, pp. 554-568, April, 2003.

21. G. Campardo, R. Micheloni, “Special Issue on Flash Memory Technology [Scanning the Issue]”, Proceedings of the IEEE, Volume 91, Issue 4, pp. 483-488, April, 2003.

20. O. Khouri, R. Micheloni, G. Campardo, G. Torelli, “Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories”, Journal of Analog Integrated Circuits and Signal Processing, 34, pp. 119-131, Kluwer Academic Publishers, 2003.

19. S. Gregori, A. Cabrini, O. Khouri, R. Micheloni, G. Torelli, “High-Accuracy Program Scheme for Multilevel Flash Memories”, Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Krakow, Poland, Sept. 1-4, 2003.

18. O. Khouri, A. Cabrini, S. Gregori, R. Micheloni, G. Torelli, “Voltage-Mode Closed-Loop Sense Amplifier for Multilevel Flash Memories”, Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Krakow, Poland, Sept. 1-4, 2003.

17. R. Micheloni, O. Khouri, S. Gregori, A. Cabrini, G. Campardo, L. Fratin, G. Torelli, “A 0.13-mm CMOS NOR Flash Memory Experimental Chip for 4-b/cell Digital Storage”, Proceedings of the 28th European Solid-State Circuit Conference (ESSCIRC), pp. 131-134, September, 2002.

16. O. Khouri, S. Gregori, A. Cabrini, R. Micheloni, G. Torelli, “Improved charge pump for flash memory applications in triple-well cmos technology”, Proceedings of the International Symposium on Industrial Electronics (ISIE), Vol. 4, pp. 1322-1326, 2002.

15. S. Gregori, O. Khouri, R. Micheloni, G. Torelli, "An error control code scheme for multilevel flash memories", Proceedings of the 2001 IEEE International Workshop on Memory Technology, Design and Testing (MTDT), San Jose, CA, USA, pp. 45-49, August, 2001.

14. O. Khouri, S. Gregori, D. Soltesz, G. Torelli, "Low output resistance charge pump for flash memory programming", Proceedings of the 2001 IEEE International Workshop on Memory Technology, Design and Testing (MTDT), San Jose, CA, USA, pp. 99-104, August, 2001.

13. R. Micheloni, I. Motta, O. Khouri, G. Torelli, “Stand-By Low-Power Architecture in a 3V-Only 2-Bit/Cell 64-Mbit Flash Memory”, Proceedings of the 8th International Conference on Electronics, Circuits and Systems, vol. II, pp. 929-932, September, 2001.

12. G. Campardo, R. Micheloni, “Architecture of non volatile memory with multi-bit cells” – Microelectronic Engineering, Vol. 59, No. 1-4, pp. 173-181, November, 2001.

11. G. Campardo, R. Micheloni, “Architecture of Non Volatile Memory with Multi-bit cells”, Proceedings of the 12th Insulating Films on Semiconductors (INFOS ), Udine, June, 2001.

10. O. Khouri, R. Micheloni, A. Sacco, “Program Word-Line Voltage Generator for Multilevel Flash Memories”, Proceedings of the 7th International Conference on Electronics, Circuits and Systems, vol. II, pp. 1030 – 1033, December, 2000.

9. S. Gregori, P. Ferrari, R. Micheloni, G. Torelli, “Construction of Polyvalent Error Control Codes for Multilevel Memories”, Proceedings of the 7th International Conference on Electronics, Circuits and Systems, vol. II, pp. 751 – 754, December, 2000.

8. A. Pierin, S. Gregori, O. Khouri, R. Micheloni, G. Torelli, “High-Speed Low-Power Sense Comparator for Multilevel Flash Memories”, Proceedings of the 7th International Conference on Electronics, Circuits and Systems, vol. II, pp. 759 – 762, December, 2000.

7. G. Campardo, R. Micheloni et al., “40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash memory” – IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, pp. 1655-1667, November, 2000.

6. R. Micheloni, M. Zammattio, G. Campardo, O. Khouri, G. Torelli, "Hierarchical Sector Biasing Organization for Flash Memories", Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing (MTDT), San Jose, CA, USA, pp. 29-33, August, 2000.

5. O. Khouri, R. Micheloni, S. Gregori, G. Torelli, "Fast voltage Regulator for Multilevel Flash Memories", Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing (MTDT), San Jose, CA, USA, pp. 34-38, August, 2000.

4. G. Campardo, R. Micheloni et al., “A 40mm2 3V 50MHz 64Mb 4-level cell NOR-type Flash memory”, Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 274-275, February, 2000.

3. O. Khouri, R. Micheloni, I. Motta, G. Torelli, “Word-line read voltage regulator with capacitive boosting for multimegabit multilevel Flash memories”, Proceedings of the European Conference on Circuit Theory and Design (ECCTD), pp. 145-148, Stresa, Italy, September, 1999.

2. O. Khouri, R. Micheloni, G. Torelli, “Very fast recovery word-line voltage regulator for multilevel nonvolatile memories”, Proceedings of the Third IMACS/IEEE International Multiconference on Circuits, Systems, Communications and Computers (CSCC), pp. 3781-3784, Athens, Greece, June, 1999.

1. R. Micheloni, M.S. Thesis: Heterojunction photodiode for the detection of single photons in the near infrared, supported by Politecnico of Milan and the Italian Research Council (CNR), Milan, Italy, October, 1994.