Patents

144. US11934696: Machine Learning Assisted Quality Of Service (QoS) For Solid State Drives

143. US11,699,493: Method And Apparatus For Performing A Read Of A Flash Memory Using Predicted Retention-and-read-disturb-compensated Threshold Voltage Shift Offset Values

142. US11,514,994: Method And Apparatus For Outlier Management 

141. US11,514,992: Method And Apparatus For Reading A Flash Memory Device  

140. US11,398,291: Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device 

139. US10,891,083: System and method for randomizing data

138. US10,630,317: Method for performing error corrections of digital information codified as a symbol sequence

137. US10,332,613: Nonvolatile memory system with retention monitor

136. US10,291,263: Auto-learning log likelihood ratio

135. US10,283,215: Nonvolatile memory system with background reference positioning and local reference positioning

134. US10,230,396: Method and apparatus for layer-specific LDPC decoding

133. US10,157,677: Background reference positioning and local reference positioning using threshold voltage shift read

132. US10,152,273: Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend

131. US9,899,092: Nonvolatile memory system with program step manager and method for program step management

130. US9,892,794: Method and apparatus with program suspend using test mode

129. US9,886,214: Nonvolatile memory system with erase suspend circuit and method for erase suspend management

128. US9,813,080: Layer specific LDPC decoder

127. US9,799,405: Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction

126. US9,747,200: Memory system with high speed non-volatile memory backup using pre-aged flash memory devices

125. US9,590,656: System and method for higher quality log likelihood ratios in LDPC decoding

124. US9,454,414: System and method for accumulating soft information in LDPC decoding

123. US9,450,610: High quality log likelihood ratios determined using two-index look-up table

122. US9,448,881: Memory controller and integrated circuit device for correcting errors in data read from memory cells

121. US9,417,804: System and method for memory block pool wear leveling

120. US9,397,701: System and method for lifetime specific LDPC decoding

119. US9,305,661: Nonvolatile memory system that uses programming time to reduce bit errors

118. US9,235,467: System and method with reference voltage partitioning for low density parity check decoding

117. US9,128,858: Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values

116. US9,092,353: Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

115. US8,990,661: Layer specific attenuation factor LDPC decoder

114. US8,971,112: Method of programming a multi-level memory device

113. US8,966,335: Method for performing error corrections of digital information codified as a symbol sequence

112. US8,707,122: Nonvolatile memory controller with two-stage error correction technique for enhanced reliability

111. US8,694,855: Error correction code technique for improving read stress endurance

110. US8,694,849: Shuffler error correction code system and method

109. US8,656,257: Nonvolatile memory controller with concatenated error correction codes

108. US8,621,318: Nonvolatile memory controller with error detection for concatenated error correction codes

107. US8,572,361: Configuration of a multilevel flash memory device

106. US8,553,462: Method of programming a multi-level memory device

105. US8,397,144: BCH data correction system and method

104. US8,347,201: Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code

103. US8,065,467: Non-volatile, electrically-programmable memory

102. US7,937,576: Configuration of a multi-level flash memory device

101. US7,908,543: Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code

100. US7,889,586: Circuit and method for retrieving data stored in semiconductor memory cells

99. US7,863,967: Multistage regulator for charge-pump boosted voltage applications

98. US7,777,466: Voltage regulator or non-volatile memories implemented with low-voltage transistors

97. US7,730,357: Integrated memory system

96. US7,719,894: Method of programming cells of a NAND memory device

95. US7,630,238: Page buffer for multi-level NAND electrically-programmable semiconductor memories

94. US7,592,849: Level shifter for semiconductor memory device implemented with low-voltage transistors

93. US7,581,153: Memory with embedded error correction codes

92. US7,532,061: Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile flash memories

91. US7,529,136: Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations

90. US7,521,983: High-voltage switch with low output ripple for non-volatile floating-gate memories

89. US7,499,345: Non-volatile memory implemented with low-voltages transistors and related system and method

88. US7,499,332: Circuit and method for electrically programming a non-volatile semiconductor memory via an additional programming pulse after verification

87. US7,474,577: Circuit and method for retrieving data stored in semiconductor memory cells

86. US7,444,543: Data control unit capable of correcting boot errors, and corresponding self-correction method

85. US7,408,819: Semiconductor memory device with a page buffer having an improved layout arrangement

84. US7,394,694: Flash memory device with NAND architecture with reduced capacitive coupling effect

83. US7,382,660: Method for accessing a multilevel nonvolatile memory device of the flash NAND type

82. US7,366,014: Double page programming system and method

81. US7,362,616: NAND flash memory with erase verify based on shorter evaluation time

80. US7,349,265: Reading method of a NAND-type memory device and NAND-type memory device

79. US7,336,538: Page buffer circuit and method for multi-level NAND programmable memories

78. US7,328,397: Method for performing error corrections of digital information codified as a symbol sequence

77. US7,260,005: Data bus architecture for a semiconductor memory

76. US7,221,602: Memory system comprising a semiconductor memory

75. US7,221,212: Trimming functional parameters in integrated circuits

74. US7,184,348: Sensing circuit for a semiconductor memory

73. US7,184,319: Method for erasing non-volatile memory cells and corresponding memory device

72. US7,068,540: Method and device for programming an electrically programmable non-volatile semiconductor memory

71. US7,035,142: Non volatile memory device including a predetermined number of sectors

70. US7,031,193: Method and device for programming an electrically programmable non-volatile semiconductor memory

69. US7,027,317: Semiconductor memory with embedded DRAM

68. US7,017,099: Method for error control in multilevel cells with configurable number of stored bits

67. US6,956,773: Circuit for programming a non-volatile memory device with adaptive program load control

66. US6,947,329: Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices

65. US6,944,072: Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory device

64. US6,922,366: Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device

63. US6,901,011: Self-repair method via ECC for nonvolatile memory devices, and relative nonvolatile memory device

62. US6,891,755: Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors

61. US6,871,258: METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE

60. US6,836,442: Nonvolatile memory device having a voltage booster with a discharge circuit activated during standby

59. US6,829,168: Power supply circuit structure for a row decoder of a multilevel non-volatile memory device

58. US6,822,905: Regulation method for the source terminal voltage in a non-volatile memory cell during a program phase and corresponding program circuit

57. US6,809,961: Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit

56. US6,788,579: Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude

55. US6,728,141: Method and circuit for timing dynamic reading of a memory cell with control of the integration time

54. US6,724,658: Method and circuit for generating reference voltages for reading a multilevel memory cell

53. US6,674,385: Analog-to-digital conversion method and device, in high-density multilevel non-volatile memory devices

52. US6,650,173: Programmable voltage generator

51. US6,646,913: Method for storing and reading data in a multilevel nonvolatile memory

50. US6,643,179: Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell

49. US6,642,776: Bandgap voltage reference circuit

48. US6,639,833: Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics

47. US6,603,681: Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method

46. US6,574,146: Circuit and method for timing multi-level non-volatile memories

45. US6,559,627: Voltage regulator for low-consumption circuits

44. US6,542,404: Small size, low consumption, multilevel nonvolatile memory

43. US6,532,171: Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units

42. US6,515,911: Circuit structure for providing a hierarchical decoding in semiconductor memory devices

41. US6,504,758: Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding

40. US6,493,268: Circuit device for performing hierarchic row decoding in non-volatile memory devices

39. US6,493,260: Nonvolatile memory device, having parts with different access time, reliability, and capacity

38. US6,480,421: Circuit for reading non-volatile memories

37. US6,456,530: Nonvolatile memory device with hierarchical sector decoding

36. US6,456,527: Nonvolatile multilevel memory and reading method thereof

35. US6,456,150: Circuit for biasing a bulk terminal of a MOS transistor

34. US6,437,636: Low consumption voltage boost device

33. US6,433,583: CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching

32. US6,424,121: Voltage generator switching between alternating, first and second voltage values, in particular for programming multilevel cells

31. US6,418,051: Non-volatile memory device with configurable row redundancy

30. US6,404,273: Voltage booster with a low output resistance

29. US6,373,780: Single supply voltage nonvolatile memory device with row decoding

28. US6,356,481: Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages

27. US6,351,413: Nonvolatile memory device, in particular a flash-EEPROM

26. US6,327,184: Read circuit for a nonvolatile memory

25. US6,320,790: Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase

24. US6,307,778: Non volatile memory with detection of short circuits between word lines

23. US6,307,396: Low-consumption TTL-CMOS input buffer stage

22. US6,301,152: Non-volatile memory device with row redundancy

21. US6,301,149: Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory

20. US6,259,635: Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories

19. US6,259,632: Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories

18. US6,249,112: Voltage regulating circuit for a capacitive load

17. US6,237,104: Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory

16. US6,181,602: Device and method for reading nonvolatile memory cells

15. US6,169,423: Method and circuit for regulating the length of an ATD pulse signal

14. US6,157,579: Circuit for providing a reading phase after power-on-reset

13. US6,157,225: Driving circuit with three output levels, one output level being a boosted level

12. US6,144,589: Boosting circuit, particularly for a memory device

11. US6,128,225: Method and circuit for reading low-supply-voltage nonvolatile memory cells

10. US6,122,200: Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector

9. US6,111,809: Line decoder for a low supply voltage memory device

8. US6,094,073: Line decoder for memory devices

7. US6,075,750: Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory

6. US6,069,837: Row decoder circuit for an electronic memory device, particularly for low voltage applications

5. US6,018,255: Line decoder for memory devices

4. US5,946,238: Single-cell reference signal generating circuit for reading nonvolatile memory

3. US5,903,498: Low-supply-voltage nonvolatile memory device with voltage boosting

2. US5,886,925: Read circuit and method for nonvolatile memory cells with an equalizing structure

1. US5,805,500: Circuit and method for generating a read reference signal for nonvolatile memory cells