Guide: Dr. Anu Gupta, Assistant Professor, EEE Group, BITS, Pilani
The serial to parallel converter is a part of a bigger SoC (System on Chip) that has a processor sitting inside it and uses this block to communicate serially with the outside world. This block converts an input serial stream into a parallel based on certain register configurations.
The CPU uses a Bus Interface to configure this block and control the data transfer across the chip. This block samples in serial data on the serial clock received by it. The toggling of the serial clock indicates valid data on the data line. The block samples 16 bit serial data for 16 clock cycles and holds the previous data in latches which are available for the CPU to read .This implementation has a unique feature of no interruption of serial data while the previous data is read.
The project involves the design of the above module, using verilog. The design is then verified for the expected functionalities using RC compiler and SOC Encounter.
MODULE SPECIFICATION:
A. Signal Definition
1. Bus Interface
· Gated Input Clock of 66.67 MHz (obtained after clock tree synthesis in Encounter)
· Worst Case Slack : 2.764ns (obtained after clock tree synthesis in Encounter)
· Enable for the module/block
· Write data bus
· Read data bus
2. Clocks, Resets & Global Signals
· Asynchronous Reset
3. Serial Interface
· Serial Data Input
· Serial Data Clock.