Design of a 10 Bit DAC

Guide: Dr. Anu Gupta, Assistant Professor, EEE Group, BITS, Pilani

Design Procedure:

Design of the differential pair of Op-Amp was the first step which has been started with plotting of I_d/(W/L) vs V_ov and G_m/ I_d vs V_ov graphs for both NMOS and PMOS transistors. The values of current and overdrives are fixed roughly based on the power dissipation and output swing aimed. The W/L values are taken from the graphs and transistors are designed. After a few iterations targeting maximum gain with required f_-3dB, the first stage is optimized. Later a similar procedure is followed for the second stage as well. Here R-C compensation is used to decrease the effect of second pole on phase margin. The improvement of phase margin is due to a negative zero introduced in between the two poles.

Note: Click on the figures to enlarge.