Current Position: Staff Engineer, Intel Optane Group, Intel Corporation, Santa Clara, CA

Education

• PhD in Electrical and Computer Engineering, Purdue University, IN, USA, (Aug, 2016)

• Masters in Electrical and Computer Engineering, Purdue University, IN, USA, (May, 2011)

• B.E. (Hons.) Electrical & Electronics Engineering, Birla Institute of Technology & Science, Pilani, India, (May, 2009)

Professional Interests: Semiconductor Device Physics, Modeling and Characterization, Solar Cells, Novel Solid-state Memory technologies, Phenomenological modeling, Statistics, Reliability

Research Highlight

1. Review article highlighted on cover page of Progress in Photovoltaics April, 2018 issue.

R. V. K. Chavali, S. De Wolf, and M. A. Alam, "Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review", Prog. in Photovoltaics, April 2018 (link)

The cover image, by Raghu V. K. Chavali et al., is based on the Research Article Device physics underlying silicon heterojunction and passivating‐contact solar cells: A topical review, DOI: 10.1002/pip.2959. Image Credit: Research Publication Services, King Abdullah University of Science and Technology.

2. "Physics model acts as an 'EKG' for solar panel health", an article in Green Energy & Tech. September 2018 issue was based on journal article I co-authored.

Citing research: X. Sun, R. V. K. Chavali, and M. A. Alam, "Real‐time monitoring and diagnosis of photovoltaic system degradation only using maximum power point—the Suns‐Vmp method", Prog. in Photovoltaics, July. 2018

3. Best Student Paper Finalist at 42nd IEEE PVSC 2015 for R. V. K. Chavali, E. C. Johlin, J. L. Gray, T. Buonassisi and M. A. Alam, “Process-to-Panel Modeling for a-Si/c-Si Heterojunction Solar Cells,” in Photovoltaic Specialists Conference 42nd IEEE, 2015.

4. Best Poster Award at 40th IEEE PVSC 2014 for R. V. K. Chavali and J. L. Gray, “Numerical Method to Separate the Photo-Current and Contact Injection Current in Solar Cells,” at Photovoltaic Specialists Conference 40th IEEE, 2014.

In the Purdue ECE spotlight for Best Poster Award at 40th IEEE PVSC

5. Best Student Paper Finalist at 40th IEEE PVSC 2014 for R. V. K. Chavali, S. Khatavkar, B. M. Arora, P. Nair, J. Gray, and M. Alam, Multi-Probe Characterization of Inversion Charge for Parameterization of HIT^TM Cells,” at Photovoltaic Specialists Conference 40th IEEE, 2014.

6. Solar Energy Research Institute for India and the United States (SERIIUS) research highlights

Several of my research works were highlighted in SERIIUS quarterly research highlights to DOE, USA and DST India.

Multiscale Modeling & Reliability:

• Process-to-Panel Modeling of Silicon Heterojunction Technology

• HIT-Perovskite Bifacial Tandem to Produce Output Power > 330 W/m²

• A Multiprobe Analysis to Triangulate the HIT Cell Parameters

• Integrated Modeling

• A Multiprobe Analysis to Identify the Performance Bottlenecks in HIT Cell

7. Awarded AMD Design Contest Award for Full custom Design of Voltage Over Scaling by Unbalanced Pipelining, Case Study: 8-Bit Wallace Tree Multiplier at Purdue University, 2009.