International Conference Papers

Total Documents: 19

2016 (11)

  1. T. Adiono, R.F. Armansyah, S.S. Nolika, F.D. Ikram, R.V.W. Putra, & A.H. Salman. Visible Light Communication System for Wearable Patient Monitoring Device. IEEE TENCON. Marina Bay Sands, Singapore. November 2016. (to appear) (Link-1) (Link-2)

  2. R.F. Armansyah, S.S. Nolika, N. Dewanti, T.L.R. Mengko, R.V.W. Putra, & T. Adiono. A Facial Expression Recognition Method using Morphological Operation and Fuzzy Classification. 2nd International Conference on Electrical Engineering and Computer Science (ICEECS). Taipei, Taiwan. October 2016. (to appear) (Link-1) (Link-2)

    1. T. Adiono, A. Pradana, R.V.W. Putra, & Y. Aska. Experimental Evaluation for PWM and OFDM Based Visible Light Communication. 2nd International Conference on Electrical Engineering and Computer Science (ICEECS). Taipei, Taiwan. October 2016. (to appear) (Link-1) (Link-2)

  3. T. Adiono, A. Pradana, R.V.W. Putra, & S. Fuada. Analog Filters Design in VLC Analog Front-End Receiver for Reducing Indoor Ambient Light Noise. 13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Jeju, South Korea. October 2016. (to appear) (Link-1) (Link-2)

    1. T. Adiono, M.Y. Fathany, R.V.W. Putra, K. Afifah, M.H. Santriaji, B.L. Lawu, & S. Fuada. Live Demonstration: MINDS – Meshed and Internet Networked Devices System for Smart Home. 13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Jeju, South Korea. October 2016. (to appear) (Link-1) (Link-2)

    2. T. Adiono, R.F. Armansyah, F.D. Ikram, S.S. Nolika, R.V.W. Putra, & A.H. Salman. Parallel Morphological Template Matching Design for Efficient Human Detection Application. International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). Phuket, Thailand. October 2016. (to appear) (Link-1) (Link-2)

  1. T. Adiono, M.D. Adhinata, N. Prihatiningrum, R. Disastra, R.V.W. Putra, & A.H. Salman. An Architecture Design of SAD Based Template Matching for Fast Queue Counter in FPGA. International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). Phuket, Thailand. October 2016. (to appear) (Link-1) (Link-2)

    1. Prasetyo, R.V.W. Putra, T. Adiono, & A.H. Salman. Kurtosis and Energy Based Spectrum Detection for SDR Based RF Monitoring System. International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). Phuket, Thailand. October 2016. (to appear) (Link-1) (Link-2)

  1. T. Adiono, R.V.W. Putra, M.Y. Fathany, B.L. Lawu, K. Afifah, M.H. Santriaji, & S. Fuada. Prototyping Design of Electronic End-Devices for Smart Home Application. The IEEE Region 10 Symposium (Tensymp). Bali, Indonesia. May 2015. (http://dx.doi.org/10.1109/TENCONSpring.2016.7519415) (Link-1) (Link-2)

  2. B.L. Lawu, M.Y. Fathany, K. Afifah, M.H. Santriaji, R.V.W. Putra, S. Fuada, & T. Adiono. Prototyping Design of Mechanical Based End-Devices for Smart Home Application. The 4th International Conference on Information and Communication Technology (ICoICT). Bandung, Indonesia. May 2015. (http://dx.doi.org/10.1109/ICoICT.2016.7571927) (Link-1) (Link-2)

  3. R. V. W. Putra & T. Adiono. Hybrid Multi System-on-Chip Architecture: A Rapid Development Design for High-Flexibility System. The 2016 International Conference on Electronics, Information, and Communication (ICEIC). Danang, Vietnam. January 2016. (http://dx.doi.org/10.1109/ELINFOCOM.2016.7562962) (Link-1) (Link-2)

2015 (3)

  1. T. Adiono, R. V. W. Putra, M.Y. Fathany, M.A. Wibisono, & W. Adijarto. Smart Home Platform Based on Optimized Wireless Sensor Network Protocol and Scalable Architecture. The 9th International Conference on Telecommunication System, Services, and Applications (TSSA). Bandung, Indonesia. November 2015. (to appear) (Link-1) (Link-2)

  2. R. V. W. Putra & T. Adiono. Optimized Hardware Algorithm for Integer Cube Root Calculation and Its Architecture. The 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). Bali, Indonesia. November 2015. (http://dx.doi.org/10.1109/ISPACS.2015.7432777) (Link-1) (Link-2)

  3. R. V. W. Putra & T. Adiono. The Refined mCBE Algorithm for Efficient Constants Multipliers Architecture. The 12th International SoC Design Conference (ISOCC). Gyeongju, South Korea. November 2015. (http://dx.doi.org/10.1109/ISOCC.2015.7401670) (Link-1) (Link-2)

2014 (2)

  1. R. V. W. Putra & T. Adiono. A Register-Free and Homogenous Architecture for Square Root Algorithm. The 2014 International Conference on Computer, Control, Informatics and Its Applications (IC3INA). Bandung, Indonesia. October 2014. (http://dx.doi.org/10.1109/IC3INA.2014.7042602) (Link-1) (Link-2)

  2. R. V. W. Putra & T. Adiono. A Configurable and Low Complexity Hard-Decision Viterbi Decoder in VLSI Architecture. The 2nd International Conference on Information and Communication Technology (ICoICT). Bandung, Indonesia. May 2014. (http://dx.doi.org/10.1109/ICoICT.2014.6914062) (Link-1) (Link-2)

2013 (2)

  1. R. V. W. Putra. A Novel Fixed-Point Square Root Algorithm and Its Digital Hardware Design. The 2013 International Conference on ICT for Smart Society (ICISS), Jakarta, Indonesia. June 2013. (http://dx.doi.org/10.1109/ICTSS.2013.6588110) (Link-1) (Link-2)

  2. R. V. W. Putra. VLSI Design of Parallel Sorter Based on Modified PCM Algorithm and Batcher's Odd-Even Mergesort. The 2013 International Conference on ICT for Smart Society (ICISS), Jakarta, Indonesia. June 2013. (http://dx.doi.org/10.1109/ICTSS.2013.6588108) (Link-1) (Link-2)

2011 (1)

  1. R. V. W. Putra, R. Mareta, N. Anbarsanti, & T. Adiono. The Efficient mCBE Agorithm and Quantization Numbers for Multiplierless and Low Complexity DCT/IDCT Image Compression Architecture. The 2011 International Conference on Electrical Engineering and Informatics (ICEEI), Bandung, Indonesia. July 2011. (http://dx.doi.org/10.1109/ICEEI.2011.6021774) (Link-1) (Link-2)