Rachmad V. W. Putra
I received Bachelor of Science (B.Sc.) degree on Electrical Engineering (2007-2012*) and Master of Science (M.Sc.) on Electronics Engineering (2013-2015*) with a distinction Cum Laude, both from Institut Teknologi Bandung / Bandung Institute of Technology (ITB), Indonesia. I was an intern at CV. Versatile Silicon Technologies, Indonesia in 2010. I was both, a full-time and a part-time engineer at PT. Fusi Global Teknologi, Indonesia in 2 terms of period for almost 2 years (2012-2014*). I was working as teaching assistant at Electrical Engineering Department, School of Electrical Engineering and Informatics ITB and research assistant at Microelectronics Center ITB (2012-2017*). Currently, I'm working as project research assistant and pursuing Ph.D. at Computer Architecture and Reliable Energy-Efficient Technologies (CARE-Tech.) Research Group, Embedded Computing Systems (ECS), Institute of Computer Engineering, Faculty of Informatics, Vienna University of Technology / Technische Universität Wien (TU Wien), Vienna, Austria. My research interests spread in various topic of electronic systems including VLSI / IC Design, System-on-Chip (SoC), Computer Architecture, Internet-of-Things and Optical Wireless Communications.
Education
Dr. Techn. (... on going)
[2017 - now]
Computer Architecture and Robust Energy-Efficient Technologies (CARE-Tech.)
Embedded Computing Systems
Institute of Computer Engineering
Faculty of Informatics
Technische Universität Wien, Austria
Thesis
(... on going)
Supervisor: Prof. Dr.-Ing. Muhammad Shafique
Master of Science (M.Sc.)
[2013 - 2015]
Electronics Engineering
School of Electrical Engineering and Informatics
Institut Teknologi Bandung / Bandung Institute of Technology, Indonesia
Thesis
Hybrid Multi System-on-Chip (H-MSoC) Architecture: Design and Implementation
Supervisor: Trio Adiono, PhD
Bachelor of Science (B.Sc.)
[2007 - 2012]
Electrical Engineering
School of Electrical Engineering and Informatics
Institut Teknologi Bandung / Bandung Institute of Technology, Indonesia
Thesis
Reconfiguration of OpenSPARC T1 8-Cores Processor to Low-Cost Single-Core Processor
Supervisor: Trio Adiono, Ph.D
Email: rachmad at pme dot itb dot ac dot id
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* period of position