Broad View: As-grown array has metallic (m) as well as semiconducting (s) single wall carbon nanotube (SWNTs) with diameter distribution ranging from 0.5 nm to 3.5 nm. Our studies establish a method by which high density aligned-array of s-SWNTs (in chemically pristine form with mobility of 1500 cm2/V-S) are available as channel materials for logic applications at sub-10 nm technology node. Surround-gate geometry has better electrostatic control over tri-gate FinFET, therefore, has a prospect to fit in 14 nm/10 nm technology node. We work on self-heating and reliability of surround-gate nanowire FET.
New approaches to selectively remove the m-SWNTs from as-grown array
The material properties of the carbon nanotubes are extra-ordinary such as ultrathin body (0.5 nm-3.5 nm), high mobility (1500 cm2/V-S), etc. Low drive current due to limited cross-section is overcome by utilizing the tubes in aligned array configuration. The widely used methods for synthesizing carbon nanotubes (1) arc discharge, (2) laser ablation, and (3) chemical vapor deposition. Irrespective of all growth methods, the contamination of semiconducting tubes by metallic SWNT (1:2 ratio) in the array have frustrated applications in high performance electronics. Additional processing is necessary to improve the ratio of the semiconducting to metallic tubes. High temperature removal of m-SWNTs degrades performance by damaging s-SWNTs. A thin organic coating over the array allows low temperature removal. Self-heating of the metallic nanotubes patterns the organic coating.
1) We design partial-gate FET through 3D self-consistent model (between Poisson and drift-diffusion) to systematically turn-off the s-SWNTs. Inappropriate geometry and bias initiate the undesired tunneling leakage (BTBT).
2) Wireless (microwave heating) input makes the method convenient and scalable, and allows wafer scale m-SWNTs removal. Appropriate source/drain contacts work-function can suppress the current through the s-SWNTs. Through 3D electrical transport we explore the effectiveness of six different source/drain contacts (Pd, Au, Mo, etc.) to turn-off the s-SWNTs.
Related Publications:
[4] X. Xie, M. A. Wahab, Y. Li, A. E. Islam, B. Tomic, J. Huang, B. Burns, E. Seabron, S. N. Dunham, F. Du, J. Lin, W. L. Wilson, J. Song, Y. Huang, M. A. Alam, and J. A. Rogers, “Direct Current Injection and Thermocapillarity for Purification of Aligned Arrays of Single-Walled Carbon Nanotubes,” Journal of Applied Physics, vol. 117, p. 134303, 2015. [LINK] In the News: AIP.org, Phys.org,Science Daily, Nano Werk, EurekAlert, Nanotechnology Now
[3] X. Xie*, S. H. Jin*, M. A. Wahab*, A. E. Islam, C. Zhang, F. Du, E. Seabron, T. Lu, S. N. Dunham, H. I. Cheong, Y.-C. Tu, Z. Guo, H. U. Chung, Y. Li, Y. Liu, J.-H. Lee, J. Song, Y. Huang, M. A. Alam, W. L. Wilson, and J. A. Rogers, ”Microwave Purification of Large-Area Horizontally Aligned Arrays of Single-Walled Carbon Nanotubes”, Nature Communications, 2014. (*equal contribution) [LINK] In the news: Purdue ECE Spotlight
[2] S. H. Jin, S. N. Dunham, J. Song, X. Xie, J. Kim, C. Lu, A. Islam, F. Du, J. Kim, J. Felts, Y. Li, F. Xiong, M. A. Wahab, M. Menon, E. Cho, K. L. Grosse, D. J. Lee, H. U. Chung, E. Pop, M. A. Alam, W. P. King, Y. Huang, and J. A. Rogers, ”Using Nanoscale Thermocapillary Flows to Create Purely Semiconducting Arrays of Single Walled Carbon Nanotubes”, Nature Nanotechnology, vol. 8, no. 5, pp. 347-355, 2013. [LINK] In the News: Nature News and Views, nanotechweb.org, McCORMICK News
[1] M. A. Wahab*, S. H. Jin*, A. E. Islam, J. Kim, J. Kim, W.-H. Yeo, D. J. Lee, H. U. Chung, J. A. Rogers, and M. A. Alam,”Electrostatic Dimension of Aligned-Array Carbon Nanotube Field-Effect Transistors”, ACS Nano, vol. 7, no. 2, pp. 1299-1308, 2013. (*equal contribution) [LINK]
Correlated breakdown in aligned-array of carbon nanotubes due to electrostatic crosstalk
Any (process-induced) broken/incomplete single-wall carbon nanotube (SWNT) in aligned arrays can affect the neighboring SWNTs through electrostatic cross-talk. Once the induced localized electric-field exceeds a critical field (~23 V/µm), it triggers band-to-band-tunneling and impact-ionization currents in the affected tube; the SWNT now burns at a voltage much lower than one would expect for an isolated nanotube. Combining electrical transport with Monte-Carlo we analyze correlated breakdown.
Related Publications:
[2] M. A. Wahab and M. A. Alam, ”Implications of Electrical Crosstalk for High Density Aligned Array of Single-Wall Carbon Nanotubes”, IEEE Trans. Electron Devices, 2014 (Early Access). [LINK] [IEEE highlights as Popular Article, Oct 2014]
[1] M. A. Wahab and M. A. Alam, ”Electrostatic Cross-Talk to Define the Density Limit of Aligned-Array Phase-Change-Memory with Carbon Nanotube Electrodes.”, 72nd Device Research Conference (DRC), pp. 91-92, June 22-25, 2014, CA, USA. [LINK]
Electrostatics control of gate over SWNT density
The partial-gate FET used to remove the m-SWNTs can also be applied to electrostatically dope the s-SWNTs. We showed that with the increase of SWNT density, both ON and OFF currents per nanotube vary by orders of magnitude.
Related Publications:
[1] M. A. Wahab*, S. H. Jin*, A. E. Islam, J. Kim, J. Kim, W.-H. Yeo, D. J. Lee, H. U. Chung, J. A. Rogers, and M. A. Alam,”Electrostatic Dimension of Aligned-Array Carbon Nanotube Field-Effect Transistors”, ACS Nano, vol. 7, no. 2, pp. 1299-1308, 2013. (*equal contribution) [LINK]
Carbon nanotube optoelectronics
In order to increase the carrier injection asymmetric metal contacts with aligned array SWNTs is a good choice. In this work, we analyze such device with 3D electrical transport. Exciton mediated electron–hole recombination near the lower work-function contact is the dominant source of photon emission. High current thresholds for electroluminescence in these devices result from diffusion and quenching of excitons near the metal contact. Key findings are: (i) EL occurs near the lower work-function contact, (ii) EL has a large current threshold, and (iii) EL parameters (such as VT, VT,EL) are characterized by statistical distributions.
Related Publications:
[1] X. Xie*, A. E. Islam*, M. A. Wahab*, L. Ye, X. Ho, M. A. Alam, and J. A. Rogers, ”Electroluminescence in Aligned-Array Single-Wall Carbon Nanotubes with Asymmetric Contacts”, ACS Nano, vol. 6, no. 9, pp. 7981-7988, 2012. (*equal contribution) [LINK]
Performance of strained ballistic carbon nanotube transistor
We evaluated the performance metrics (ON-current, OFF-current, ON/OFF current ratio, subthreshold slope, transconductance, intrinsic cut-off frequency, etc.) of ballistic carbon nanotube transistors (CNTFET) for coaxial geometry. We obtain electrostatic potential by solving two dimensional Poisson’s equation in cylindrical coordinates. For charge density calculation, we use recursive Green’s function algorithm to solve non-equilibrium Green’s function equations. Schottky barrier and MOSFET like source/drain contacts, strained CNT channel, single-wall and double-wall CNTs, etc., are considered. Performance improves with strain and MOSFET like contact shows improved performance.
Related Publications:
[4] M. A. Wahab and Q. D. M. Khosru, ”Strain Effects on the Performance of Zero-Schottky-Barrier Double-Walled Carbon Nanotube Transistors”, Journal of Applied Physics, vol. 108, no. 3, pp. 034301(1-8), 2010. [LINK]
(Also appears in Virtual Journal of Nanoscale Science and Technology, Aug 16, 2010)
[3] M. A. Wahab and K. Alam, ”Performance of Zero-Schottky-Barrier and Doped Contacts Single and Double Walled Carbon Nanotube Transistors”, Japanese Journal of Applied Physics, vol. 49, no. 2, pp. 025101(1-6), 2010. [LINK]
(Also appears in Virtual Journal of Nanoscale Science and Technology, Mar 8, 2010)
[2] M. A. Wahab and K. Alam, ”Performance Comparison of Zero-Schottky-Barrier and Doped Contacts Carbon Nanotube Transistors with Strain Applied”, Nano-Micro Letters, vol. 2, no. 2, pp. 126-133, 2010. [LINK, Springer]
[1] M. A. Wahab, ”Strain Effect on Single and Double Walled Carbon Nanotubes”, Proc. of IEEE International Technical Conference (IEEE TENCON 2009), November 23-26, 2009, Singapore. [LINK]
Variability and reliability of 3D transistor
Increased transistor density in the IC worsens the self-heating. This heating is further degraded due to narrow heat flow path from the FinFET. Therefore, temperature effect on the degradation (NBTI, TDDB, etc.) can’t be ignored. Through 3D electrical and thermal transport we analyzed the degradation.
Related Publications:
[7] M. A. Wahab, S. H. Shin, and M. A. Alam, “Spatio-Temporal Mapping of Device Temperature due to Self-Heating in Sub-22 nm Transistors,” IEEE Int. Reliability Physics Symposium (IRPS), pp. XT.5.1-XT.5.6, Apr 17-21, 2016, Pasadena, CA, USA. [LINK]
[6] M. A. Wahab, S. H. Shin, and M. A. Alam, “3D Modeling of Spatio-Temporal Heat-Transport in III-V Gate-All-Around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature,” IEEE Trans. Electron Devices, vol. 62, pp. 3595-3604, 2015. [LINK] [IEEE highlights as Popular Article, Oct 2015]
[5] S. H. Shin, M. A. Wahab, M. Masuduzzaman, K. Maize, J. J. Gu, M. Si, A. Shakouri, P. D. Ye, and M. A. Alam, “Direct Observation of Self-heating in III-V Gate-All-Around Nanowire MOSFETs,” IEEE Trans. Electron Devices, vol. 62, pp. 3516-3523, 2015. (Special Issue) [LINK]
[4] S. H. Shin, M. A. Wahab, W. J. Ahn, A. Ziabari, K. Maize, A. Shakouri, and M. A. Alam, “Fundamental trade-off between Short-Channel Control and Hot Carrier Degradation in an ETSOI Technology,” IEEE Int. Electron Devices Meeting (IEDM), pp. 20.3.1-20.3.4, Dec 7-9, 2015, Washington DC, USA. [LINK]
[3] S. H. Shin, M. Masuduzzaman, M. A. Wahab, K. Maize, J. J. Gu, M. Si, A. Shakouri, P. D. Ye, and M. A. Alam, “Direct Observation of Self-heating in III-V Gate-All-Around Nanowire MOSFETs,” IEEE Int. Electron Devices Meeting (IEDM), pp. 20.3.1-20.3.4, Dec 15-17, 2014, San Francisco CA, USA. [LINK]
[2] S. H. Shin, M. A. Wahab, M. Masuduzzaman, M. Si, J. J. Gu, P. D. Ye, and M. A. Alam, ”Origin and Implications of Hot Carrier Degradation of Gate-All-Around Nanowire III-V MOSFETs”, IEEE International Reliability Physics Symposium (IRPS), pp. 4A.3.1-4A.3.6, June 1-5, 2014, HI, USA. [LINK]
[1] S. H. Shin, M. Masuduzzaman, J. J. Gu, M. A. Wahab, N. Conrad, M. Si, P. D. Ye, and M. A. Alam, ”Impact of Nanowire Variability on Performance and Reliability of Gate-All-Around III-V MOSFETs”, IEEE International Electron Devices Meeting (IEDM), pp. 7.5.1-7.5.4, December 9-11, 2013, Washington DC, USA. [LINK]
Compact Model of Negative Capacitance Transistor
We developed the compact model of short-channel (sub-45 nm) NC-FET and evaluated the DC and Transient performance of the basic circuits such as NC-FET CMOS Inverter, SRAM, etc.
Related Publications:
[4] M. A. Wahab and M. A. Alam, “A Verilog-A Compact Model for Negative Capacitance FET,” NEEDs NanoHUB, 2015. [LINK] (Users: 440)
[3] M. A. Wahab and M. A. Alam, “MATLAB: Negative Capacitance FET,” NEEDs NanoHUB, 2015. [LINK] (Users: 850)
[2] M. A. Wahab and M. A. Alam, “Compact Model of Short-Channel Negative Capacitance (NC)- FET with BSIM4/MVS and Landau Theory,” NEEDS Annual Meeting and Workshop, May 11-12, 2015, Cambridge, MA, USA.
[1] M. A. Alam*, P. Dak*, M. A. Wahab*, and X. Sun*, “Physics-based Compact Models for Insulated-Gate Field-Effect Biosensors, Landau-Transistors, and Thin-Film Solar Cells,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-8, Sep 28-30, 2015, CA, USA. (*equal contribution) (Invited) [LINK]