Present Position (from April 1st, 2020)

• Human Brain Project, <Networks underlying  brain cognition and consciousness> WorkPackage, Deputy Leader

• National Coordinator of the INFN project HBP_WaveScales and Permanent Staff Researcher at  INFN Roma, Ape Massive Parallel Computers Design Group

Previous Positions

• Human Brain Project, Deputy Leader, Cognitive and Systems Neuroscience (SubProject 3) (2016-2020)

• Coordinator of the WaveScalES experiment, WP3.2 in the the Human Brain Project  (2016-2020)

• Coordinator of the European Collaboratve Project EURETILE: EUropean REference TIled architecture Experiment (2010-2014)

• Coordinator of the European Integrated FP6 Project SHAPES: Scalable Software Hardware Architecture Platform for Embedded Systems (2006-2009)

• CTO, Atmel Roma design center (2000-2010). 

  • Architect of Diopsis 740 and Diopsis 940 MPSoCs (ARM + mAgic VLIW DSP)

  • Architect of mAgic/mAgicV VLIW floating-point DSP Core 

• Permanent Staff Researcher (part-time) INFN Roma, Ape Massive Parallel Computers Design Group 

• Since 1984, member of the INFN APE (1984-1988), APE100 (1989-1994) and APEmille (1995-2000) design teams of Massive Parallel/Distributed Computers

• Co-Founder of IPITEC (Intellectual Property Initiative for Tools and Embedded Cores) (1997-2000)

• EUREKA DIAM !2390 Project - Italian Coordinator

• Architecture Responsible of the ESPRIT FP4 European Project mAgic-FPU 27000 (1997-2000)

• Promoting Member, BRINSAR (Brain Inspired Architectures) Research Organization

• 2015-03-17: NEWS on european commission about EURETILE results:

• https://ec.europa.eu/digital-agenda/en/news/many-tile-hardware-software-brain-simulation-and-embedded-systems-euretile-fet-proactive

Keywords about activities of Pier Stanislao PAOLUCCI: 

• Human Brain Project, SP3 WaveScalES

• DPSNN - STDP: Distributed Spiking Neural Net simulator with Spike Timing Dependent Plasticity 

• EURETILE European FP7 Research Project (2010-2014) 

• INFN APE SIMD Massive Parallel Computing Project (Ape Home Page)

• SHAPES European FP6 Research Project (2006-2009)

• ATMEL Diopsis 740 and Diopsis 940 (ARM + mAgic DSP)  MPSoC

• ATMEL mAgic and mAgicVLIW Floating Point DSP Core

• DIAM (Digital AM) EUREKA !2390 Project (2000-2006)

• mAgic FP4 ESPRIT 2700 Project (Music and antenna applications ASIC-based general-purpose IC-core floating point unit) - From 1998-03-01 to 2000-08-31

• MADE: Modular Architecture/Application Development Environment (Science Direct portal)

• DyProDe Patent: Dynamic Program Decompression Device for VLIW Program Compression

• Cubed Sphere: simulation of spherical problems on next-neighbors parallel computer topologies

• SIMD Matrix Transposition on next-neighbors topologies

• SIMD FFT on next neighbors topologies 

• Evolving Grammars and Dynamic Parsers (ACM portal)

• Zz Parser

• TAO Programming Language

• Esprit 27000 mAgicg-FIPU

• DIAM Digital AM Radio Eureka

• Neural Networks on next neighbors topologies

• Fully connected systems on next neighbors topologies

Partial List of Patents, Publications on Scientific Journals/Conference Proceedings (partially updated after 2003)

For an updated list of publication see

• scholar.google user link: http://scholar.google.it/citations?user=jhvLaT8AAAAJ

Patents

 US7,437,540 Patent (14 Oct 2008) P.S. Paolucci et al.  " Complex Domain Floating-Point VLIW DSP with Dat/Progra, Bus Multiplexer and Microprocessor Interface" about mAgic VLIW Floating point DSP and Diopsis 740 RISC+VLIW MPSoC architectures (downloadable from the Patents page).

 US 6,766,439 Patent (20 Jul 2004) P.S. Paolucci "Apparatus and Method for Dynamic Program Decompression" about SW Compression and HW Decompression of VLIW Program (downloadable from the Patents page) 

Publications/Presentations

Hereafter a partial list of publications

• Celotto, M., et al. Analysis and Model of Cortical Slow Waves Acquired with Optical Techniques. Methods Protoc. 2020, 3, 14 https://doi.org/10.3390/mps3010014

• Bio-intelligenza artificiale. PS Paolucci. Asimmetrie 27, 38-39 (2019) 10.23801/asimmetrie.2019.27.9

• Scaling of a Large-Scale Simulation of Synchronous Slow-Wave and Asynchronous Awake-Like Activity of a Cortical Model With Long-Range Interconnections E Pastorelli, C Capone, F Simula, MV Sanchez-Vives, P Del Giudice, et al.  Frontiers in Systems Neuroscience (2019) 13, 33. https://doi.org/10.3389/fnsys.2019.00033

• Sleep-like slow oscillations improve visual classification through synaptic homeostasis and memory association in a thalamo-cortical model. C Capone, P Elena, B Golosio, PS Paolucci. Scientific Reports 9 1 (2019) https://www.nature.com/articles/s41598-019-45525-0

• NaNet: a Reconfigurable PCIe Network Interface Card Architecture for Real-time Distributed Heterogeneous Stream Processing in the NA62 Low Level Trigger. P Cretaro, F Lo Cicero, A Lonardo, M Sozzi, R Piandani, A Biagioni, ... PoS, 118 (2019 )

• Analysis pipeline for extracting features of cortical slow oscillations G De Bonis, M Dasilva, A Pazienti, MV Sanchez-Vives, M Mattia, ... Frontiers in Systems Neuroscience 13, 70 (2019) doi:10.3389/fnsys.2019.00070

• Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems F Simula, E Pastorelli, PS Paolucci, M Martinelli, A Lonardo, A Biagioni, ... 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), Pavia, Italy, 2019. 10.1109/EMPDP.2019.8671627 

• Analysis and Model of Cortical Slow Waves Acquired with Optical Techniques M Celotto, C De Luca, P Muratore, F Resta, ALA Mascaro, F Pavone, ... arXiv preprint arXiv:1811.11687 (2018)

•  Real-time heterogeneous stream processing with NaNet in the NA62 experiment R Ammendola, M Barbanera, A Biagioni, P Cretaro, O Frezza, G Lamanna, ... Journal of Physics: Conference Series 1085 (3), 032022

• Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development M Katevenis, R Ammendola, A Biagioni, P Cretaro, O Frezza, FL Cicero, ... Microprocessors and Microsystems 61, 58-71 9 (2018) https://doi.org/10.1016/j.micpro.2018.05.009

• Gaussian and exponential lateral connectivity on distributed spiking neural network simulation E Pastorelli, PS Paolucci, F Simula, A Biagioni, F Capuani, P Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Luca Pontisso, Piero Vicini, Roberto Ammendola 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP) 10.1109/PDP2018.2018.00110

• Parallel Computing is Everywhere S Bassini, M Danelutto, P Dazzi IOS Press 2 (2018

•  The INFN COSA Project: Low-Power Computing and Storage Daniele Cesini, Elena Corni, Antonio Falabella, Andrea Ferraro, Luca Lama, Lucia Morganti, Enrico Calore, Sebastiano Fabio Schifano, Michele Michelotto, Roberto Alfieri, Roberto De Pietri, Tommaso Boccali, Andrea Biagioni, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Piero Vicini.  Advances in Parallel Computing 32, 770-779 1 2018 https://doi.org/10.3233/978-1-61499-843-3-770

• Large Scale Low Power Computing System – Status of Network Design in ExaNeSt and EuroExa Projects. Roberto Ammendola, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Francesco Simula, Piero Vicini. Advances in Parallel Computing 32, 750-759 1 2018 https://doi.org/10.3233/978-1-61499-843-3-750

• The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States Piero Vicini Roberto Ammendola, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Francesco Simula. Advances in Parallel Computing 32, 760-769 1 2018 https://doi.org/10.3233/978-1-61499-843-3-760

• Real-time track-less Cherenkov ring fitting trigger system based on Graphics Processing Units R Ammendola, A Biagioni, S Chiozzi, P Cretaro, A Cotta Ramusino, Stefano Di Lorenzo, R Fantechi, M Fiorini, O Frezza, A Gianoli, Gianluca Lamanna, F Lo Cicero, A Lonardo, M Martinelli, I Neri, PS Paolucci, E Pastorelli, R Piandani, M Piccini, L Pontisso, D Rossetti, F Simula, M Sozzi, P Vicini. Nuclear Instruments and Methods in Physics Research Section A: Accelerators , Spectrometers, Detectors and Associated Equipment 2017https://doi.org/10.1016/j.nima.2017.02.031

•  Latest generation interconnect technologies in APEnet+ networking infrastructure R Ammendola, F Lo Cicero, A Lonardo, P Cretaro, A Biagioni, O Frezza, ... J. Phys. Conf. Ser. 898, 082035 1 2017 10.1088/1742-6596/898/8/082035

• Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project R Ammendola, F Chaix, M Katevenis, A Biagioni, PS Paolucci, F Pisani, ... J. Phys. Conf. Ser. 898, 082045 1 2017 10.1088/1742-6596/898/8/082045

• The next generation of exascale-class systems: The ExaNeSt project R Ammendola, A Biagioni, P Cretaro, O Frezza, FL Cicero, A Lonardo, ... 2017 Euromicro Conference on Digital System Design (DSD), 510-515 12 2017 10.1109/DSD.2017.20

• Development of Network Interface Cards for TRIDAQ systems with the NaNet framework R Ammendola, A Biagioni, P Cretaro, S Di Lorenzo, M Fiorini, O Frezza, ... Journal of Instrumentation 12 (03), C03037 10.1088/1748-0221/12/03/C03037

• GPU-based low-level trigger system for the standalone reconstruction of the ring-shaped hit patterns in the RICH Cherenkov detector of NA62 experiment R Ammendola, A Biagioni, S Chiozzi, P Cretaro, AC Ramusino, ... Journal of Instrumentation 12 (03), C03005 2017 

• Graphical processors for HEP trigger systems R Ammendola, A Biagioni, S Chiozzi, AC Ramusino, S Di Lorenzo, ... Nuclear Instruments and Methods in Physics Research Section A: Accelerators …

• Co-designed Innovation and System for Resilient Exascale Computing in Europe: From Applications to Silicon (EuroEXA) G George, K Nectarios, P Nikela, N Konstantinos, K Vasilis, A Chloe, ... 2017 

• Power-efficient computing: experiences from the COSA project D Cesini, E Corni, A Falabella, A Ferraro, L Morganti, E Calore, ... Scientific Programming 2017 9 2017

• Reconfigurable PCI Express cards for low-latency data transport in HEP experiments R Ammendola, A Biagioni, PS Paolucci, F Lo Cicero, O Frezza, P Vicini, ... Nuovo Cim. 40, 73 2017 

• GPU real-time processing in NA62 trigger system R Ammendola, A Biagioni, S Chiozzi, P Cretaro, S Di Lorenzo, R Fantechi, ... Journal of Physics: Conference Series 800 (1), 012046 2017

•  Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms PS Paolucci, A Biagioni, LG Murillo, F Rousseau, L Schor, L Tosoratto, ... Journal of Systems Architecture 69, 29-53 17 2016 

• The exanest project: Interconnects, storage, and packaging for exascale systems M Katevenis, N Chrysos, M Marazakis, I Mavroidis, F Chaix, N Kallimanis, ... 2016 Euromicro Conference on Digital System Design (DSD), 60-67 33 2016 

• Graphics Processing Units for HEP trigger systems R Ammendola, M Bauce, A Biagioni, S Chiozzi, AC Ramusino, R Fantechi, ... Nuclear Instruments and Methods in Physics Research Section A: Accelerators … 3 2016 

• GPU-based Real-time Triggering in the NA62 Experiment R Ammendola, A Biagioni, P Cretaro, S Di Lorenzo, R Fantechi, M Fiorini, ... arXiv preprint arXiv:1606.04099 3 2016 

• NaNet-10: a 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector. R Ammendola, A Biagioni, M Fiorini, O Frezza, A Lonardo, G Lamanna, ... Journal of Instrumentation 11 (03), C03030 15 2016 IEEE: 

• GPU-based Low-Level Trigger System for Real-Time Cherenkov Ring Fitting R Ammendola, M Martinelli, L Pontisso, L Tosoratto, O Frezza, M Sozzi, ..

• Graphics processors in hep low-level trigger systems R Ammendola, A Biagioni, S Chiozzi, AC Ramusino, P Cretaro, ... EPJ Web of Conferences 127, 00011 1 2016

• NaNet3: The on-shore readout and slow-control board for the KM3NeT-Italia underwater neutrino telescope R Ammendola, A Biagioni, O Frezza, FL Cicero, M

* E. Pastorelli, et al., "Scaling to 1024 software processes and hardware cores of the distributed simulation of a spiking neural network including up to 20G synapses", (2015) arXiv:1511.09325, http://arxiv.org/abs/1511.09325

* E. Pastorelli, et al., "Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses", (2015) arXiv:1512.05264,  http://arxiv.org/abs/1512.05264

* P.S. Paolucci, et al. "Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores", (2015), http://arxiv.org/abs/arXiv:1505.03015

* R. Ammendola, et al., "Graphics Processing Units for HEP trigger systems", Nuclear Instruments and Methods in Physics Research Section A, (2015), http://dx.doi.org/10.1016/j.nima.2015.11.106

* P.S. Paolucci et al., "Dynamic Many-process Applications on Many-tile Embedded Systems and HPC Clusters: the EURETILE programming environment and execution platforms", Journal of Systems Architecture, Available online 24 November 2015, ISSN 1383-7621, http://dx.doi.org/10.1016/j.sysarc.2015.11.008.

* S. Wesner et al., "Special Section on Terascale Computing", Future Generation Computer Systems, vol. 53 (2015) pag. 88-89, http://dx.doi.org/10.1016/j.future.2015.07.015

* R. Ammendola et al., "ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces", Future Generation Computer Systems, vol. 53 (2015) pag. 109-118, http://dx.doi.org/10.1016/j.future.2014.12.012

* R. Ammendola et al., "A hierarchical watchdog mechanism for systemic fault awareness on distributed systems", Future Generation Computer Systems, vol. 53 (2015) pag. 90-99, http://dx.doi.org/10.1016/j.future.2014.12.015

* A. Lonardo et al., "NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing", Journal of Instrumentation, vol. 10 (2015), http://dx.doi.org/10.1088/1748-0221/10/04/C04011

* R. Ammendola et al., Architectural improvements and technological enhancements for the APEnet+ interconnect system", Journal of Instrumentation, vol. 10 (2015), http://dx.doi.org/10.1088/1748-0221/10/02/C02005

* R. Ammendola et al., "A multi-port 10GbE PCIe NIC featuring UDP offload and GPUDirect capabilities.", Journal of Physics, Conference Series, vol 664 (2015), http://dx.doi.org/10.1088/1742-6596/664/9/092002

* R. Ammendola et al, "Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system", Journal of Physics, Conference Series, vol 664 (2015), http://dx.doi.org/10.1088/1742-6596/664/9/092017

* R. Ammendola, et al., "Fast algorithm for real-time rings reconstruction", (2015) GPU Computing in High-Energy Physics (GPUHEP2014) : Pisa, Italy. http://dx.doi.org/10.3204/DESY-PROC-2014-05/42

* A. Lonardo et al., "A FPGA-based Network Interface Card with GPUDirect enabling real-time GPU computing in HEP experiments", (2015) GPU Computing in High-Energy Physics (GPUHEP2014) : Pisa, Italy, September 2014, http://dx.doi.org/10.3204/DESY-PROC-2014-05/16

* R. Ammendola, et al., "GPUs for the realtime low-level trigger of the NA62 experiment at CERN" (2015) , GPU Computing in High-Energy Physics (GPUHEP2014) : Pisa, Italy, http://dx.doi.org/10.3204/DESY-PROC-2014-05/15

* R. Ammendola et al., "LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System," in Reliable Distributed Systems (SRDS), 2014 IEEE 33rd International Symposium on, pp.265-270, http://dx.doi.org/10.1109/SRDS.2014.33

* L. Schor et al., "EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications onto Many-Tile Systems", Parallel and Distributed Processing with Applications (ISPA), 2014 IEEE Int. Symp. on, (2014) pag. 182-189,  http://dx.doi.org/10.1109/ISPA.2014.32

* P.S. Paolucci, et al., "EURETILE D7. 3-Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes" (2014) arxiv:1408.4587, http://arxiv.org/abs/1408.4587

* A. Lonardo, et al., "NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features", (2014)  arXiv:1406.3568 [physics.ins-det], http://arxiv.org/abs/1406.3568

* G. Lamanna et al., "GPUs for real-time processing in HEP trigger systems", Journal of Physics: Conference Series,   vol. 513, (2014), International Conference on Computing in High Energy and Nuclear Physics (CHEP) 2013, http://dx.doi.org/10.1088/1742-6596/513/1/012017

* R. Ammendola et al., “Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network“, Journal of Physics: Conference Series, vol. 513, (2014), Workshop on Advanced Computing & Analysis Techniques in Physics Research (ACAT) 2013, http://dx.doi.org/10.1088/1742-6596/523/1/012013

* S, Chiozzi, et al., "GPUs for Online Processing in Low-Level Trigger Systems", (2014), http://inspirehep.net/record/1360142/files/PoS(TIPP2014)208.pdf

* R. Ammendola et al., "NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs“, in JINST, Journal of Instrumentation, vol. 9 (2014), Proceedings of Topical Workshop on Electronics for Particle Physics (TWEPP) 2013, IOP Publishing, 2013, http://dx.doi.org/10.1088/1748-0221/9/02/C02023.

* R. Ammendola, et al., "Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems, (2014) Journal of Physics: Conference Series vol. 513 (5), http://dx.doi.org/10.1088/1742-6596/513/5/052002

* A. Biagioni, et al., "Evolution of FPGA-based network acceleration for GPUs", poster at the conference Perspectives of GPU Computing in Physics and Astrophysics, Rome, Italy, September 15-17, 2014 

* A. Biagioni, et al., "Development of a GPU aware NIC: from HPC to HEP experiments", poster at the conference (GTC) GPU Technology Conference, March 24-26, 2013 - San Jose (California) 

* P.S. Paolucci, et al., "Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a mini app benchmark", Poster at the Workshop 'Dagli atomi al cervello', Politecnico di Milano, 27 Jan 2014

* M. Bauce, et al., "GPUs for Online Processing in Low-Level Trigger Systems", Proceedings of Science (TIPP2014) Technology and Instrumentation in Particle Physics 2014, http://inspirehep.net/record/1360142/files/PoS(TIPP2014)208.pdf

* R. Ammendola et al., "NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs" (2014) Journal of Instrumentation vol. 9 (2), http://dx.doi.org/10.1088/1748-0221/9/02/C02023

* R. Ammendola et al. "Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface" (2013) Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, IEEE, http://dx.doi.org/10.1109/ReConFig.2013.6732275

* R. Ammendola et al. "Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities", (2013) Field-Programmable Technology (FPT), 2013 International Conference on,  http://dx.doi.org/10.1109/FPT.2013.6718331

* R. Ammendola, et al. "APEnet+ 34 Gbps data transmission system and custom transmission logic" (2013) Journal of Instrumentation 8 (12), C12022, http://dx.doi.org/10.1088/1748-0221/8/12/C12022

* P.S. Paolucci, et al. "Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster" (2013) arXiv:1310.8478 [cs.DC], http://arxiv.org/abs/1310.8478

* R. Ammendola, et al., "A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report" (2013) arXiv:1307.1270 [cs.DC], http://arxiv.org/abs/1307.1270

* R. Ammendola, et al., "'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale" (2013)  arXiv:1307.0433 [cs.DC], http://arxiv.org/abs/1307.0433

* R. Ammendola, et al., "GPU peer-to-peer techniques applied to a cluster interconnect", (2013)  Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International, http://dx.doi.org/10.1109/IPDPSW.2013.128

* Paolucci, P.S., Bacivarov, I., Goossens, G., Leupers, R., Rousseau, F., Schumacher, C., Thiele, L., Vicini, P., "EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment", (2013), arXiv:1305.1459 [cs.DC] , http://arxiv.org/abs/1305.1459 - then published as ISBN: 978-88-908488-0-3 (2013), http://dx.doi.org/10.12837/2013T01

* R. Ammendola, et al. "APEnet+: a 3D Torus network optimized for GPU-based HPC Systems" (2012) Journal of Physics: Conference Series 396 (4), 042059, http://dx.doi.org/10.1088/1742-6596/396/4/042059

* R. Ammendola, et al., "A 34 Gbps data transmission system with FPGAs embedded transceivers and QSFP+ modules" (2012) Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE, http://dx.doi.org/10.1109/NSSMIC.2012.6551230

* S. Amerio, et al., "Applications of GPUs to online track reconstruction in HEP experiments", (2012) Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE, http://dx.doi.org/10.1109/NSSMIC.2012.6551422

* A. Biagioni, et al. "The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture" (2012) arXiv:1203.1536 [cs.AR], http://arxiv.org/abs/1203.1536

* R. Ammendola, et al., "APEnet+: High Bandwidth 3D Torus direct network for petaflops scale commodity clusters", (2011), Journal of Physics: Conference Series 331 (5), 052029, 

 http://dx.doi.org/10.1088/1742-6596/331/5/052029 

* R. Ammendola, et al.,  "QUonG: A GPU-based HPC System Dedicated to LQCD Computing."  (2011) In Proceedings of the 2011 Symposium on Application Accelerators in High-Performance Computing (SAAHPC '11). IEEE Computer Society, Washington, DC, USA, 113-122.  http://dx.doi.org/10.1109/SAAHPC.2011.15 

* R. Ammendola, et al., "APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters" proceedings of The XXVIII International Symposium on Lattice Field Theory PoS(Lattice 2010)022 and arXiv:1012.0253v1

[70]     R. Ammendola, A. Biagioni, O. Frezza, F. Lo Cicero, A. Lonardo, P.S. Paolucci, D. Rossetti, A. Salamon, G. Salina, F. Simula, L. Tosoratto, P. Vicini - Mastering multi-GPU computing on a torus network - GPU Technology Conference 2010 (GTC)

[69] Pier Stanislao Paolucci "FP7 EURETILE Project: EUropean REference TILed architecture Experiment" HipeacInfo, Quarterly Newsletter, Number 24, page 11, October 2010 (http://www.Hipeac.net/newslette) https://sites.google.com/site/pierstanislaopaolucci/euretile/PaolucciEuretileHipeacInfo24October2010.pdf

[68] Chagoya-Garzon, A.; Guerin, X.; Rousseau, F.; Petrot, F.; Rossetti, D.; Lonardo, A.; Vicini, P.; Paolucci, P.S.; , "Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips," Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on , vol., no., pp.48-54, 23-26 June 2009

doi: http://dx.doi.org/10.1109/RSP.2009.12