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RESEARCH SUMMARY:

I am a second-year PhD student at the Computer Science and Engineering Department at the University of Michigan, Ann Arbor, USA working with Prof. Ronald Dreslinski and Prof. Trevor Mudge. I earned my undergraduate degree in Electrical and Electronics Engineering from Birla Institute of Technology & Science (BITS) Pilani, India, and a Master's degree in Electrical Engineering with thesis from the Technion - Israel Institute of Technology, Israel. As a part of my Master's thesis, I worked with Prof. Shahar Kvatinsky, and I was a member of ASIC^2 Research Group.

I am passionate about research in computer architecture, in general. More specifically, during my undergrad and master's degrees, I focused on one of the most prevalent problems in the contemporary computing systems, i.e., von Neumann bottleneck. I approached the problem through multiple directions, which include the design of low-cost and large-scale persistent memories using emerging memory technologies (i.e., ReRAM, PCM, and STT-MRAM), and processing-in-memory, which attempts to minimize the data transfer between the processing and the memory subsystems.

PUBLICATIONS:

In case this page is not up-to-date, I believe that Google Scholar is reasonably accurate.

Conference Publications

  1. N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P. E. Gaillardon, and S. Kvatinsky, "Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines," Design, Automation, and Test in Europe DATE 2018. PDF
  2. R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky. “SIMPLE MAGIC: Synthesis and In-memory Mapping of Logic Execution for Memristor Aided loGIC,” International Conference on Computer Aided Design ICCAD 2017. PDF
  3. J. Ruben, R. Ben Hur, N. Wald, N. Talati, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky. “Memristive Logic: A Framework for Evaluation and Comparison,” International Symposium on Power and Timing Modeling, Optimization, and Simulations PATMOS 2017. PDF
  4. N. Talati, Z. Wang, and S. Kvatinsky, "Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes," International Symposium on Circuits and Systems ISCAS 2017. PDF
  5. R. Ben Hur, N. Talati, and S. Kvatinsky, "Algorithmic Considerations in Memristive Memory Processing Units (MPU)," Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016 (in press). PDF (Talk- CNNA_2016_paper_36_presentation_final.pptx is available on the Publications page.)
  6. P. Mane, N. Talati, A. Riswadkar, B. Jasani, and C. Ramesha, "Implementation of NOR logic based on material implication on CMOL FPGA architecture," 28th International Conference on VLSI Design (VLSID), 2015, , pp. 523 - 528, Jan 2015. PDF (Awarded the fellowship)
  7. P. Mane, N. Talati, A. Riswadkar, R. Raghu and C.K. Ramesha, "Implicating logic functions with memristors," 11th International Conference on SoC Design (ISOCC), 2014, pp. 232 - 233, Nov 2014. PDF (Best poster award (attached at the bottom of the page)+BITSAA travel grant award)

Journal Publications

  1. N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, "Logic design within memristive memories using Memristor Aided loGIC (MAGIC)," IEEE Transactions on Nanotechnology, vol. 15, no. 4, pp. 635-650, July 2016. PDF (Please find the supplementary material on the Publications page, not available on IEEE Xplore.)
  2. P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha, "Reconfiguration on nanocrossbar using material implication," Sadhana - Academy Proceedings in Engineering Science, vol. 42, no. 1, pp. 33-44, Jan. 2017.
  3. P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha, "Stateful-NOR based reconfigurable architecture for logic implementation," Microelectronics Journal, vol. 46, no. 6, pp. 551 - 562, June 2015. PDF

Magazines

  1. N. Talati, H. Ha, B. Perach, R. Ronen, and S. Kvatinsky, "CONCEPT: A Column Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM," IEEE MICRO, vol. 39, no. 1, pp. 33-43, Jan.-Fab. 2019. PDF

Book Chapters

  1. N. Talati, R. Ben Hur, N. Wald, A. Haj Ali, J. Reuben, and S. Kvatinsky, "mMPU – a Real Processing–in–Memory Architecture to Combat the von Neumann Bottleneck," in Advanced Applications of Emerging NVM Devices, Springer Series in Advanced Microelectronics, 2017. PDF
  2. J. Reuben, N. Talati, N. Wald, R. Ben Hur, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky, "A Taxonomy and Evaluation Framework for Memristive Logic," in Handbook of Memristor Networks, Springer, 2017 (in press).

Workshop Publications

  1. S. Kvatinsky, R. Ben Hur, N. Talati, and N. Wald, "mMPU: memristive Memory Processing Unit," MEMRISYS 2017.
  2. R. Ben Hur, N. Talati, Nimrod Wald, and Shahar Kvatinsky, "Memory Processing Unit for In-Memory Processing," The First International Workshop on In-Memory and In-Storage Computing with Emerging Technologies (In Conjunction with 25th International Conference on Parallel Computing and Compilation Techniques (PACT)), 2016.

Technical Reports

  1. R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, ” Latency Optimized Mapping of Logic Functions for Memristor Aided Logic (MAGIC),” CCIT Technical Report #908, December 2016.


SCIENTIFIC PEER REVIEW ACTIVITY:

I believe that as a researcher, it is one's responsibility to get involved in the scientific peer review process to advance the current state-of-the-art. As a part of my responsibility, I am currently involved (or was involved) in the peer review process of following conferences and journals:

Conference External Review: HPCA 2018, DATE 2018, CASES 2017, ISCAS 2017, ISCAS 2016, CNNA 2016

Journal Referee: IEEE Transactions on Very Large Scale Systems (TVLSI), ACM Transactions on Architecture and Code Optimization (TACO), IEEE Transactions on Emerging Topics in Computing (TETC), IEEE Transactions on Nanotechnology (TNANO), Microelectronics Journal, Elsevier


COMMUNITY SERVICE:

I have had excellent opportunities to work at the Blind People's Association, India at Ahmedabad, twice (during the winter and summer of my freshman year)!

Thanks to Ms. Kinnari Desai for giving me this chance to serve the people with disabilities at BPA.

I was involved in organizing important government resolutions (GRs) for people with disabilities during winter, and designing a software package for organizing events at the institution during summer.

Also, thanks to my friends Vraj, Vikram, and Mit, who joined and helped me in this noble cause.

CONTACT:

Address:

2765 BBB - Computer Science & Engineering

University of Michigan,

Ann Arbor, MI - 48105

E-mail:

nishil dot talatiwork at gmail dot com or

talatin at umich dot edu

Please do NOT spam or distribute my email address to a third party without my consent.

Last updated: October, 2018.