Tutorial: Expedited Development of Novel RISC-V Instructions Through an Emulation-Simulation Framework
(Co-located with ISCA 2024)
Overview of the Tutorial
Our objective is to enhance the efficiency of designing and evaluating new instructions within the RISC-V ISA, thereby reducing the entry barriers for researchers seeking to apply RISC-V to their respective domain-specific challenges. We will provide a comprehensive explanation about our top-to-bottom evaluation framework, which enables quick design and evaluation of new RISC-V instructions going through software stack integration and performance simulation to RTL design. The instructional program will comprise a blend of informative lectures and interactive lab sessions. Initially, participants will receive a comprehensive overview of diverse tools essential for both software and hardware development tailored to platforms supporting the RISC-V ISA. Subsequently, we will delve into the specifics of our evaluation framework, elucidating the utilization of one ISA emulator (QEMU) alongside a computer architecture simulator (gem5) and one RTL simulator (verilator) coupled with the RTL model of our in-house Out-of-Order (OoO) core. Furthermore, we will elucidate the integration methodology of these tools to expedite software development of new instructions via ISA simulators and to assess the performance of the developed instructions using computer architecture simulators to finally integrate these new instructions into our OoO Core. To facilitate hands-on learning, we will furnish our evaluation framework through a docker image, encompassing the aforementioned tools, along with requisite wrappers and scripts for seamless integration. Additionally, practical exercises and example code will be provided during the lab sessions, enabling attendees to gain firsthand experience in the design, integration, and evaluation of new RISC-V instructions using our framework. Ultimately, all participants will depart equipped with the evaluation framework, code samples, and the necessary proficiency to employ them as foundational elements in their individual research endeavors.
Target Audience
The tutorial is tailored for a diverse audience, encompassing computer architecture researchers attending ISCA2024 with a keen interest in integrating the RISC-V ISA into their research endeavors, and who seek a proficient tool to commence their work within this ISA domain. Moreover, it caters to researchers already immersed in RISC-V, aiming to augment their design methodology with a comprehensive top-to-bottom evaluation framework. Hardware developers exploring avenues for expedited performance assessment of new RISC-V instructions, prior to embarking on hardware modules in RTL, will find substantial value in this tutorial. Additionally, graduate and undergraduate students with a passion for computer systems and embedded systems are well-positioned to benefit from this tutorial, as it provides hands-on coding experiences facilitating the modeling and evaluation of diverse CPU architectures.
Prerequisites: Have Docker software installed on the laptop used during the tutorial.
Please download the Docker image from the following link before the workshop:
docker pull isabenders/isca24-tutorial:latest
This docker image requires 22GB of disk space.
Overall Tutorial Schedule
ISCA_tutorial.pptxOrganizers:
Barcelona Supercomputing Center (BSC).
Universitat Politècnica de Catalunya (UPC).
University of Michigan (UM).
Julian Pavon (BSC, UPC) currently a final-year Ph.D. candidate at the Universitat Politecnica de Catalunya advised by Dr. Adrian Cristal and Dr. Osman Unsal. His research interests are centered around Computer Architecture, Vector Architectures, and RTL design. Julian's primary focus involves the design of innovative Vector Processing Units capable of accelerating applications with irregular memory access patterns across various domains, including sparse algebra, databases, and genome sequence analysis. His contributions have been published in different top-tier venues. Julian has worked designing and developing different hardware modules for multiple RISC-V cores manufactured.
Ivan Vargas Valdivieso (BSC, UPC) is a Ph.D. candidate at the Universitat Politècnica de Catalunya (UPC) and a researcher at the Barcelona Supercomputing Center (BSC), supervised by Dr. Adrian Cristal and Dr. Osman Unsal. His primary focus is on accelerating DBMS through innovative hardware-software co-design and Processing in Memory Technologies. His research interests include computer architecture, Processing in Memory, Vector Architectures, Database Management Systems, and Hardware Simulators.
Adrian Cristal (BSC) serves as a research team leader, specializing in computer architecture with a primary focus on high-performance microarchitecture, low-power computing, and reliability. Possessing a multidisciplinary background, his expertise encompasses parallel programming, benchmark development, programming models, reconfigurable computing, runtime systems, and microarchitecture design. With a substantial publication record exceeding 200 works in peer-reviewed conferences, workshops, and journals, Dr. Cristal has received five best paper conference awards, each from a pool of at least 110 submissions. Their academic impact is further evidenced by an H-index of 30, 3,240 citations, and three issued patents.
Nishil Talati (UM) is an Assistant Research Scientist (Research Faculty) at the CSE department of University of Michigan, USA. He earned his PhD from University of Michigan. His research interests include computer architecture and systems software design for improving the performance of modern data-intensive workloads. His research is published at several top-tier venues including ISCA, MICRO, HPCA, ASPLOS, among others. Nishil’s work has been recognized as the 2021 HPCA best paper award, 2023 DATE and 2023 IISWC best paper honorable mentions.