LATEST NEWS:

[November 2025] A preprint of Yuchen's new work on optimizing the workload of Novel View Synthesis (NVS) is out, check this out HERE.

[Aug 2025] Yunjie's paper on designing a scalable algorithm for graph pattern matching is accepted at VLDB 2026. Congratulations Yunjie!

[Aug 2025] Taru's paper on understanding the performance of Zero Knowedge Proofs (ZKP) on GPUs is accepted at IISWC 2025. Congratulations Taru!

[June 2025] Yuchen's paper on designing a dynamically adaptive serving system for image generation is accepted at ASPLOS 2026. Congratulations Yuchen! The preprint of the paper can be found HERE.

[June 2025] Sanjay's paper on query co-optimization for pattern matching in temporal graphs is accepted at shepherding at VLDB! Congratulations Sanjay!

MENTEES:

I am fortunate to work with these extremely talented group of students every day!

PhD Students:

• Yichao Yuan (at UIUC)

• Yuchen Xia (at UIUC)

• Thomas Mason Nelson (at Michigan)

Undergraduate/master's Students:

• Arjun Laxman (UM CSE SUGS student)

• Josh Weingarden (UM CSE undergraduate student)

• Erin Xu (UM CSE undergraduate student)

Alumni:

• Sanjay Sri Vallabh Singapuram (first employment: Waymo)

• Wynn Kaza (first employment: Apple)

• Divyam Sharma (first employment: Amazon)

• Yunjie Pan (PhD graduate; first employment: Meta)

• Advait Iyer (first employment: Tesla)

• Haojie Ye (PhD graduate; first employment: NVIDIA)

• Yuhan Chen (PhD graduate; first employment: Meta)

• Heewoo Kim (PhD graduate; first employment: CU Boulder)

• Kuan-Yu Chen (PhD graduate; first employment: Tenstorrent)

• Gaurav Shah (summer 2023 visitor, next endeavor: MS at CMU)

• Joe Su (summer 2023 visitor, next endeavor: full-time at a defense contractor)

PUBLICATIONS:

In case this page is not up-to-date, I believe that Google Scholar is reasonably accurate.

Conference Publications

1. [Preprint] Y. Xia, S. Kundu, M. Chowdhury, and N. Talati, "Sphinx: Efficiently Serving Novel View Synthesis using Regression-Guided Selective Refinement," arXiv (November 2025).
   [PDF] [Code]

2. Y. Pan, O. Bhalerao, C. Seshadhri, and N. Talati, "TIMEST: Temporal Information Motif Estimator Using Sampling Trees, " at International Conference on Very Large Data Bases VLDB 2026.
   [PDF]

3. T. Verma, Y. Yuan, N. Talati, and T. Austin, "ZKProphet: Understanding Performance of Zero-Knowledge Proofs on GPUs," at the 2025 IEEE International Symposium on Workload Characterization IISWC 2025.
   [PDF]

4. Y. Xia, D. Sharma, Y. Yuan, S. Kundu, and N. Talati, "MoDM: Efficient Serving for Image Generation via Mixture-of-Diffusion Models," at 31st Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS 2026.
   [PDF] [Code]

5. S. Singapuram, R. Dreslinski, and N. Talati, "Mayura: Expoiting Similarities in Motifs for Temporal Co-Mining," at International Conference on Very Large Data Bases VLDB 2026.
   [PDF]

6. [Preprint] Y. Yuan, L. Ma, and N. Talati, "MoE-Lens: Towards the Hardware Limit of High-Throughput MoE LLM Serving Under Resource Constraints," arXiv (April 2025)
   [PDF]

7. H. Kim, S. Singapuram, H. Ye, J. Izraelevitz, T. Mudge, R. Dreslinski, and N. Talati, "NMP-PaK: Near-Memory Processing Acceleration for Scalable De Novo Genome Assembly," at 52nd IEEE/ACM International Symposium on Computer Architecture ISCA 2025.
   [PDF]

8. A. Khadam, K. Kamalakkannan, Z. Zhu, A. Poptani, Y. Gu, J. Dominguez-Trujillo, N. Talati, D. Fujiki, S. Mahlke, G. Shipman, and R. Das, "DX100: Programmable Data Access Accelerator for Indirection," at 52nd IEEE/ACM International Symposium on Computer Architecture ISCA 2025.
   [PDF][Code]

9. Y. Yuan, A. Iyer, L. Ma, and N. Talati, "Vortex: Overcoming Memory Capacity Limitations in GPU-Accelerated Large-Scale Data Analytics," at 51st International Conference on Very Large Data Bases VLDB 2025.
   [PDF] [Code]

10. H. Ye, Y. Xia, Y. Chen, K-Y. Chen, Y. Yuan, S. Deng, B. Kasikci, T. Mudge, and N. Talati, "Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design," at the 31st IEEE International Symposium on High-Performance Computer Architecture HPCA 2025.
    [PDF] [Code]

11. A. Khadem, D. Fujiki, H. Chen, Y. Gu, N. Talati, S. Mahlke, and R. Das "Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing," at the 31st IEEE International Symposium on High-Performance Computer Architecture HPCA 2025.
    [PDF] [Code]

12. Y. Pan, O. Bhalerao, C. Seshadhri, and N. Talati, "Accurate and Fast Estimation of Temporal Motifs using Path Sampling," at International Conference on Data Mining ICDM 2024.
    [PDF] [Code]

13. Y. Xia, J. Kim, Y. Chen, H. Ye, S. Kundu, C. Hao, and N. Talati, "Understanding The Performance and Estimating The Cost Of LLM Fine-Tuning," at IEEE International Symposium on Workload Characterization IISWC 2024.
    [PDF] [Code]

14. J. Pavon, I. Valdivieso, C. Morales, C. Hernandez, M. Aslan, J. Lindegger, Y. Yuan, R. Bagué, M. Alser, O. Mutlu, S. Marco-Sola, O. Ergin, N. Talati, M. Valero, O. Unsal, A. Cristal, "QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms," at 2024 International Symposium on Computer Architecture ISCA 2024.
    [PDF]

15. Y. Chen, H. Ye, S. Vedula, A. Bronstein, R. Dreslinski, T. Mudge, and N. Talati, "Demystifying Graph Sparsification Algorithms in Graph Properties Preservation," at International Conference on Very Large Databases VLDB 2024.
    [PDF] [Code] [Supplementary Material]

16. Y. Yuan, H. Ye, S. Vedula, W. Kaza, and N. Talati, "Everest: GPU-Accelerated System for Mining Temporal Motifs," at International Conference on Very Large Databases VLDB 2024.
    [PDF] [Code]

17. A. Khadem, D. Fujiki, N. Talati, S. Mahlke, and R. Das,  "Vector Processing for Mobile Devices: Benchmark and Analysis," at IEEE International Symposium on Workload Characterization IISWC 2023. (Best Paper Honorable Mention)
    [PDF] [Code]

18. H. Kim, H. Ye, T. Mudge, R. Dreslinski, and N. Talati, "RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models," at ACM/IEEE International Symposium on Low Power Electronics and Design ISLPED 2023.
    [PDF]

19. H. Ye, S. Vedula, Y. Chen, Y. Yang, A. Bronstein, R. Dreslinski, T. Mudge, and N. Talati, "GRACE: A Scalable Graph-Based Approach To Accelerating Recommendation Model Inference," at 28th Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS 2023.
    [PDF] [Code] [Slides] [Lightning Talk]

20. Y. Chen, A. Khadem, X. He, N. Talati, T. A. Khan, T. Mudge, "PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows," at Design, Automation, and Test in Europe DATE 2023. (Best Paper Honorable Mention)
    [PDF]

21. N. Talati, H. Ye, S. Vedula, K-Y Chen, Y. Chen, D. Liu, Y. Yuan, D. Blaauw, A. Bronstein, T. Mudge, and R. Dreslinski, "Mint: An Accelerator For Mining Temporal Motifs," at the 55th IEEE/ACM International Symposium on Microarchitecture MICRO 2022.
    [PDF] [Slides]

22. L. Belayneh, H. Ye, K-Y Chen, D. Blaauw, T. Mudge, R. Dreslinski, N. Talati, "Locality-aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems," at the 31st International Conference on Parallel Architectures and Compilation Techniques PACT 2022.
    [PDF]

23. N. Talati, H. Ye, Y. Yang, L. Belayneh, K-Y Chen, D. Blaauw, T. Mudge, R. Dreslinski, "NDMiner: Accelerating Graph Pattern Mining Using Near Data Processing," at 2022 International Symposium on Computer Architecture ISCA 2022.
    [PDF] [Slides]

24. N. Talati, D. Jin, H. Ye, A. Brahmakshatriya, S. Amarasinghe, T. Mudge, D. Koutra, R. Dreslinski, "A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning," at 2021 IEEE International Symposium on Workload Characterization IISWC 2021.
    [PDF] [Code] [Full Presentation] [Slides]

25. N. Talati, K. May, A. Behroozi, Y. Yang, K. Kaszyk, C. Vasiladiotis, T. Verma, L. Li, B. Nguyen, J. Sun, J. Magnus Morton, A. Ahmadi, T. Austin, M. O'Boyle, S. Mahlke, T. Mudge, R. Dreslinski, "Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design," at the 27th IEEE International Symposium on High-Performance Computer Architecture HPCA 2021. (Best Paper Award)
    [PDF] [Full Presentation] [Short Presentation] [Slides] [UMich announcement]

26. Y. Yang, H. Ye, Y. Chen, X., Liu, N. Talati, X. He, T. Mudge, R. Dreslinski, "CoPTA: Contiguous pattern speculating TLB architecture," at International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation SAMOS 2020.
    [PDF]

27. N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P. E. Gaillardon, and S. Kvatinsky, "Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines," at Design, Automation, and Test in Europe DATE 2018.
    [PDF]

28. R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky. “SIMPLE MAGIC: Synthesis and In-memory Mapping of Logic Execution for Memristor Aided loGIC,” at International Conference on Computer Aided Design ICCAD 2017.
    [PDF]

29. J. Ruben, R. Ben Hur, N. Wald, N. Talati, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky. “Memristive Logic: A Framework for Evaluation and Comparison,” at International Symposium on Power and Timing Modeling, Optimization, and Simulations PATMOS 2017.
    [PDF]

Journal Publications

1. H. Kim, A. Amarnath, J Bagherzadeh, N. Talati, R. Dreslinski. "A Survey Describing Beyond Si Transistors, and Exploring Their Implications for Future Processors," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol 17, no. 3, pp. 1-44, June 2021.
   [PDF]

2. N. Talati, H. Ha, B. Perach, R. Ronen, S. Kvatinsky, "CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM," IEEE Micro, vol. 39, no. 1, pp. 33-43, Jan-Feb 2019.
   [PDF]

3. N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, "Logic design within memristive memories using Memristor Aided loGIC (MAGIC)," IEEE Transactions on Nanotechnology, vol. 15, no. 4, pp. 635-650, July 2016.
   [PDF] (manuscript), [PDF] (supplementary material).

4. P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha, "Reconfiguration on nanocrossbar using material implication," Sadhana - Academy Proceedings in Engineering Science, vol. 42, no. 1, pp. 33-44, Jan. 2017.

5. P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha, "Stateful-NOR based reconfigurable architecture for logic implementation," Microelectronics Journal, vol. 46, no. 6, pp. 551 - 562, June 2015.
   [PDF]

Book Chapters

1. N. Talati, R. Ben Hur, N. Wald, A. Haj Ali, J. Reuben, and S. Kvatinsky, "mMPU – a Real Processing–in–Memory Architecture to Combat the von Neumann Bottleneck," in Advanced Applications of Emerging NVM Devices, Springer Series in Advanced Microelectronics, 2017.
   [PDF]

2. J. Reuben, N. Talati, N. Wald, R. Ben Hur, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky, "A Taxonomy and Evaluation Framework for Memristive Logic," in Handbook of Memristor Networks, Springer, 2017.
   [PDF]

Workshop Publications

1. (Position paper) N. Talati, B. Kasikci, W. Zhu, and N. Sung Kim, "A Deep Co-Design Approach: Systems, Architectures, and Device Cross-Cutting Research for Energy Efficiency," DoE ASCR Energy Efficient Computing for Science Workshop 2024.
   [PDF]

2. (Position paper) J-W. Chung, N. Talati, and M. Chowdhury, "Toward Cross-Layer Energy Optimizations in AI Systems,"  DoE ASCR Energy Efficient Computing for Science Workshop 2024.
   [PDF]

3. N. Talati, Z. Wang, and S. Kvatinsky, "Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes," International Symposium on Circuits and Systems ISCAS 2017.
   [PDF]

4. S. Kvatinsky, R. Ben Hur, N. Talati, and N. Wald, "mMPU: memristive Memory Processing Unit," MEMRISYS 2017.

5. R. Ben Hur, N. Talati, and S. Kvatinsky, "Algorithmic Considerations in Memristive Memory Processing Units (MPU)," Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016.
   [PDF]

6. R. Ben Hur, N. Talati, Nimrod Wald, and Shahar Kvatinsky, "Memory Processing Unit for In-Memory Processing," The First International Workshop on In-Memory and In-Storage Computing with Emerging Technologies (In Conjunction with 25th International Conference on Parallel Computing and Compilation Techniques (PACT)), 2016. 

7. P. Mane, N. Talati, A. Riswadkar, B. Jasani, and C. Ramesha, "Implementation of NOR logic based on material implication on CMOL FPGA architecture," 28th International Conference on VLSI Design (VLSID), 2015, , pp. 523 - 528, Jan 2015.
   [PDF] (Travel grant award)

8. P. Mane, N. Talati, A. Riswadkar, R. Raghu and C.K. Ramesha, "Implicating logic functions with memristors," 11th International Conference on SoC Design (ISOCC), 2014, pp. 232 - 233, Nov 2014.
   [PDF] (Best poster award + BITSAA travel grant award)

Technical Reports

1. R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, ” Latency Optimized Mapping of Logic Functions for Memristor Aided Logic (MAGIC),” CCIT Technical Report #908, December 2016.
   [PDF]

CONTACT:

Address:

4116 Siebel Center for Computer Science

201 North Goodwin Avenue

Urbana, IL - 61801

E-mail:

nishil at illinois dot edu

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