What can remote access hardware trojan do to a Network-on-Chip?
The threat of Hardware Trojans (HTs) penetrating complex hardware systems such as multi/many-core systems is increasing due to the increasing presence of third-party players in a System-on-chip (SoC) design. Interconnection networks play a crucial role in these systems and ensure high performance by enabling data transfer among the processing cores, caches, memory, and peripherals. Given the criticality of the interconnects, the system can be severely subverted if the interconnection is compromised. Even by deploying naïve HTs, an adversary can exploit the Network-on-Chip (NoC) backbone of the processor and get access to communication patterns in the system. This information, if leaked to an attacker, can reveal important insights regarding the application suites running on the system; thereby compromising the user privacy and paving the way for more severe attacks on the entire system. In this project, me and my collaborators are exploring opportunities in designing undetectable HTs that can be embedded in the NoC routers and is capable of leaking sensitive information to an external malicious attacker through an accomplice application. We are also building inference models using deep learning that uses this leaked data to determine applications running on the multicore system. Furthermore, to protect against such attacks, we are also designing a defense mechanism.
Publications:
[1] Mountford T, Dhavlle A, Tevebaugh A, Mansoor N, Dinakarrao SMP, Ganguly A. Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips. Journal of Low Power Electronics and Applications. 2023; 13(3):50. doi:10.3390/jlpea13030050
[2] A. Dhavlle, M. M. Ahmed, N. Mansoor, K. Basu, A. Ganguly and S. M. Pudukotai Dinakarrao, "Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 12, pp. 4681-4694, Dec. 2023, doi: 10.1109/TCAD.2023.3278618
[3] M. M. Ahmed, A. Dhavlle, N. Mansoor, S. M. P. Dinakarrao, K. Basu and A. Ganguly, "What Can a Remote Access Hardware Trojan do to a Network-on-Chip?," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401297
[4] M. Meraj Ahmed et al., "Defense Against on-Chip Trojans Enabling Traffic Analysis Attacks," 2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Kolkata, India, 2020, pp. 1-6, doi: 10.1109/AsianHOST51057.2020.9358250
Robust and Dynamic Medium Access Control for Wireless Network-on-Chip Architecture
Network-on-Chip (NoC) has emerged as the enabling technology for catering to the communication needs of high-performance applications in modern multi-core System-on-Chips (SoCs). Novel interconnect technologies like on-chip photonic interconnect, multi-band RF transmission line interconnects (RFI), and wireless interconnects are some promising and emerging interconnect technologies to overcome the limitations of the metal/dielectric-based interconnection paradigm. Among, these alternatives, wireless interconnect operating in millimeter wave (mm-wave) band is a nearer-term solution due to its CMOS compatible integration of the underlying enabling technology of miniature antennas and transceivers. However, utilizing the full potential of the novel mm-wave interconnect technology in a wireless NoC (WiNoC) requires overcoming two critical design challenges: i) design of efficient, simple, and fair medium access control (MAC) mechanism and ii) managing the wireless bandwidth effectively. These requirements are very important for large multicore and multichip systems as they are designed to cater to a wide variety of applications with different communication characteristics. Furthermore, scheduling the applications on these systems to improve power and computational efficiency imposes a dynamic requirement on the network resources. In this project, we focus on designing novel techniques for designing dynamic wireless interconnection for NoCs with an efficient, simple, and fair MAC mechanism that is aware of the dynamically varying traffic demands imposed by the applications.
Publications:
[1] S. Saxena, D. S. Manur, N. Mansoor, A. Ganguly, "Scalable and energy efficient wireless inter chip interconnection fabrics using THz-band antennas," Journal of Parallel and Distributed Computing, Volume 139, 2020, Pages 148-160, doi:10.1016/j.jpdc.2020.02.002.
[2] N. Mansoor, A. Vashist, M M. Ahmed, M. S. Shamim, S. A. Mamun, A. Ganguly, "A Traffic-Aware Medium Access Control Mechanism for Energy-Efficient Wireless Network-on-Chip Architectures", https://arxiv.org/abs/1809.07862
[3] N. Mansoor, M. S. Shamim, and A. Ganguly. 2016. A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip. In Proceedings of the 18th System Level Interconnect Prediction Workshop (SLIP '16). Association for Computing Machinery, New York, NY, USA, Article 8, 1–8. doi: 10.1145/2947357.2947361
[4] N. Mansoor and A. Ganguly. 2015. Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism. In Proceedings of the 9th International Symposium on Networks-on-Chip (NOCS '15). Association for Computing Machinery, New York, NY, USA, Article 13, 1–8. doi: 10.1145/2786572.2788711
Seamless Wireless Interconnection Framework for both on and off-chip Data Communication
Computing modules in typical datacenter nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels requires data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to the internal nets of the destination chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to the limitations of the pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve communication efficiency significantly. Here, we focus on designing such a seamless interconnection network using both wired and wireless interconnects for multichip systems for dimensions spanning up to tens of centimeters.
[1] M. M. Ahmed, N. Mansoor, A. Ganguly, "A one-to-many traffic-oriented mm-wave wireless network-in-package interconnection architecture for multichip computing systems", Sustainable Computing: Informatics and Systems, Volume 26, 2020, 100379, doi: 10.1016/j.suscom.2020.100379.
PaSE: Parallel Speed-up Estimation framework of chip multiprocessors
Full-system level simulations traditionally used to evaluate the speedup of multicore systems are computationally expensive and time- consuming. On the other hand, analytical speedup models such as Amdahl’s law are powerful and fast tools to estimate the achievable speedup of these systems. However, Amdahl’s Law disregards communication among the cores. In modern multicore systems, communication latency plays a vital role in defining the overall computation time. Hence neglecting its impact results in incorrect performance measurements. To bridge this gap, we aim to design PaSE a parallel speedup estimation framework for multicore systems that considers the latency of the Network-on-Chip (NoC). To accurately capture the latency of the NoC, a queuing theory-based analytical model is required to work with an analytical speedup model. It is also important to validate the correctness of such a model with full system simulations in order to understand the accuracy of such models.
[1] G. Dharb, N. Mansoor, S. Shahriat and A. Ganguly, "PaSE: A parallel speedup estimation framework for Network-on-Chip based multicore systems," 2017 Eighth International Green and Sustainable Computing Conference (IGSC), Orlando, FL, USA, 2017, pp. 1-6, doi: 10.1109/IGCC.2017.8323601.