Research Projects

Systemic Lupus Erythematosus (SLE) poses significant challenges due to its complex and varied symptoms making diagnosis extremely challenging and time consuming. Symptoms of SLE often mimics other autoimmune or physical conditions and around 5 million people worldwide suffers from this condition, as reported by the Lupus Foundation of American during their study in 2019. However, diagnosis is much more difficult in developing countries with backdated clinical technology and setup therefore, making it virtually unknown the exact number of SLE patient count worldwide. Among all the heterogeneous symptoms presented by SLE, Butterfly Malar Rash is one of the symptoms that is prevalent in the majority of SLE patients, which is a butterfly shaped malar rash (BMR) that appears on the face. This BMR is often misdiagnosed since it is mimicked by other skin conditions like Rosacea, Acne, Eczema, Fifth disease and so on. To speed up the diagnosis process, we plan to design a deep learning models in this project to create a tool for dermatologists that can classify BMR from other similar facial rashes. 

Publications: S. Dey, N. Mansoor. "A Butterfly Malar Rash Detection Model for Early Systemic Lupus Erythematosus Diagnosis", 26th International Conference on Computer and Information Technology, 2023. DOI:10.1109/ICCIT60459.2023.10441593

The threat of Hardware Trojans (HTs) penetrating complex hardware systems such as multi/many-core systems is increasing due to the increasing presence of third-party players in a System-on-chip (SoC) design. Interconnection networks play a crucial role in these systems and ensure high performance by enabling data transfer among the processing cores, caches, memory, and peripherals. Given the criticality of the interconnects, the system can be severely subverted if the interconnection is compromised. Even by deploying naïve HTs, an adversary can exploit the Network-on-Chip (NoC) backbone of the processor and get access to communication patterns in the system. This information, if leaked to an attacker, can reveal important insights regarding the application suites running on the system; thereby compromising the user privacy and paving the way for more severe attacks on the entire system. In this project, me and my collaborators are exploring opportunities in designing undetectable HTs that can be embedded in the NoC routers and is capable of leaking sensitive information to an external malicious attacker through an accomplice application. We are also building inference models using deep learning that uses this leaked data to determine applications running on the multicore system. Furthermore, to protect against such attacks, we are also designing a defense mechanism.

Network-on-Chip (NoC) has emerged as the enabling technology for catering to the communication needs of high-performance applications in modern multi-core System-on-Chips (SoCs). Novel interconnect technologies like on-chip photonic interconnect, multi-band RF transmission line interconnects (RFI), and wireless interconnects are some promising and emerging interconnect technologies to overcome the limitations of the metal/dielectric-based interconnection paradigm. Among, these alternatives, wireless interconnect operating in millimeter wave (mm-wave) band is a nearer-term solution due to its CMOS compatible integration of the underlying enabling technology of miniature antennas and transceivers. However, utilizing the full potential of the novel mm-wave interconnect technology in a wireless NoC (WiNoC) requires overcoming two critical design challenges: i) design of efficient, simple, and fair medium access control (MAC) mechanism and ii) managing the wireless bandwidth effectively. These requirements are very important for large multicore and multichip systems as they are designed to cater to a wide variety of applications with different communication characteristics. Furthermore, scheduling the applications on these systems to improve power and computational efficiency imposes a dynamic requirement on the network resources. In this project, we focus on designing novel techniques for designing dynamic wireless interconnection for NoCs with an efficient, simple, and fair MAC mechanism that is aware of the dynamically varying traffic demands imposed by the applications.

Computing modules in typical datacenter nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels requires data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to the internal nets of the destination chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to the limitations of the pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve communication efficiency significantly. Here, we focus on designing such a seamless interconnection network using both wired and wireless interconnects for multichip systems for dimensions spanning up to tens of centimeters.

Full-system level simulations traditionally used to evaluate the speedup of multicore systems are computationally expensive and time- consuming. On the other hand, analytical speedup models such as Amdahl’s law are powerful and fast tools to estimate the achievable speedup of these systems. However, Amdahl’s Law disregards communication among the cores. In modern multicore systems, communication latency plays a vital role in defining the overall computation time. Hence neglecting its impact results in incorrect performance measurements. To bridge this gap, we aim to design PaSE a parallel speedup estimation framework for multicore systems that considers the latency of the Network-on-Chip (NoC). To accurately capture the latency of the NoC, a queuing theory-based analytical model is required to work with an analytical speedup model. It is also important to validate the correctness of such a model with full system simulations in order to understand the accuracy of such models.