Journal:
Y.L. Lin, Y.C. Chen, M.C. Lee, "Graph Neural Network-Based Glitch Rate Prediction at the Signoff Stage," ACM Transactions on Design Automation of Electronic Systems, Accepted on 05 August 2025.
M.C. Lee, Y. Shi, S.C. Chang, "Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume: 31, Issue: 7, July 2012, Page(s): 1041 - 1049.
D.C. Juan, Y.T. Chen, M.C. Lee, S.C. Chang, "An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume: 18, Issue: 2, Feb. 2010, Page(s): 246 - 255.
Conference:
S.-M. Liu, S.-Y. Fang, H.-W. Chang, M.-C. Lee, Peter Wei, "Active Learning-based Practical Power Estimation Considering Multi-Cycle Paths", Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI-2024), Taipei, Taiwan, March 2024.
M.C. Lee, Will Lin, “A New Approach Of Feed-Through Impact Estimation,” SNUG Taiwan, 2017.
Y.G. Chen, K.Y. Lai, M.C. Lee, Y. Shi, W.K. Hon and S.C. Chang, "Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits," Proc. on the Design, Automation & Test in Europe (DATE), 2014, Page(s) 1-4.
M.C. Lee, Y. Shi, Y.G. Chen, D. Marculescu, S.C. Chang, "Efficient On-Line Module-Level Wake-Up Scheduling for High Performance Multi-Module Designs," Proc. on the International Symposium on Physical Design (ISPD), 2012, Page(s): 97-104.
K.C. Wu, M.C. Lee, D. Marculescu, S.C. Chang, "Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms," Proc. on the Design, Automation & Test in Europe (DATE), 2012, Page(s): 1269 - 1274.
K.C. Wu, D. Marculescu, M.C. Lee, S.C. Chang, "Analysis and Mitigation of NBTI-Induced Performance Degradation for Power-Gated Circuits," Proc. on the International Symposium on Low Power Electronics and Design (ISLPED), 2011, Page(s): 139 - 144.
M.C. Lee, Y.G. Chen, D.K. Huang, S.C. Chang, "NBTI-aware power gating design," Proc. on the Asia and South Pacific Design Automation Conference (ASPDAC), 2011, Page(s): 609 - 614.
M.C. Lee, Y.T. Chen, Y.T. Cheng, S.C. Chang, "An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs," Proc. on the International Conference on Computer Aided Design (ICCAD), 2009, Page(s): 457 - 460.
M.C. Lee, S.C. Chang, C.S. Su, E. Tsai , "Performance and wake-up schedule optimization of power gating design," Proc. of the International SoC Design Conference (ISOCC), 2008, Volume: 01, Page(s): I-36 - 39.
Y.T. Chen, D.C. Juan, M.C. Lee, S.C. Chang, "An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon," Proc. on the International Conference on Computer Aided Design (ICCAD), 2007, Page(s): 779 - 782.
C.M. Wu, H.C. Chi, M.C. Lee, "Mapping of IP cores to network-on-chip architectures based on communication task graphs," Proc. on the International Conference on ASIC (ASICON), 2005, Volume: 2, Page(s): 953 - 956.