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Experiences:
2019.04 - now: Application Engineer, Synopsys.
2017.10 - 2019.04: Program Manager, Taiwan Semiconductor Manufacturing Company Limited.
N7 and N7+ program manager
Automotive program manager
Chip-implementation front-end designer
2013.05 - 2017.10: Senior Engineer, MediaTek Inc.
Advanced production projects on the state-of-the-art technologies
Design methodology and flow of front-end design
Synthesis tool (DesignCompiler) & flow owner
2012.08 - 2013.05: Senior Engineer, Global UniChip Corp. (GUC).
Low power design methodology on clock structure
2010.09 - 2011.05: Visiting research scholar in Dept. of ECE, Carnegie Mellon University, Pittsburgh, PA, U.S.
Reliability for power gating design
Educations:
Ph.D.: Dept. of CS, National Tsing Hua University, HsinChu, Taiwan R.O.C., 2006.09 - 2012.07.
M.S. : Dept. of CSIE, National Dong Hwa University, Hualien, Taiwan R.O.C., 2002.09 - 2004.07.
B.S. : Dept. of ICE, Chung Yuan Christian University, ChungLi, Taiwan R.O.C., 1998.09 - 2002.07.
Honors:
Graduate Students Study Abroad Program from National Science Council, Taiwan, R.O.C., 2009.
EDA Research Scholarship from SpringSoft Education Foundation, 2009.
EDA Research Scholarship from SpringSoft Education Foundation, 2007.
Interests:
VLSI electronic design automation
Low power design methodology
Power analysis and minimization for VLSI circuit
Reliability issue for VLSI circuit
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